ST STM32L4x6 Reference Manual page 93

RM0351
BANK Address 63
1FFFF800
1FFFF808
1FFFF810
Bank 2
1FFFF818
1FFFF820
User and read protection option bytes
Flash memory address: 0x1FFF 7800
ST production value: 0xFFEF F8AA
31 30 29
Res. Res. Res. Res.
15 14 13
nRST_ nRST_ nRST_
Res.
SHDW STDBY STOP
r r
Bits 31:26 Not used
Table 10. Option byte organization (continued)
[62:56] [55:48]
Unused
Unused
Unused
WRP2A
Unused
_END
WRP2B
Unused
_END
28 27 26 25
SRAM2
Res. Res.
_RST
r
12 11 10 9
Res. BOR_LEV[2:0]
r r r
Bit 25 SRAM2_RST: SRAM2 Erase when system reset
0: SRAM2 erased when a system reset occurs
1: SRAM2 is not erased when a system reset occurs
Bit 24 SRAM2_PE: SRAM2 parity check enable
0: SRAM2 parity check enable
1: SRAM2 parity check disable
Bit 23 nBOOT1: Boot configuration
Together with the BOOT0 pin, this bit selects boot mode from the Flash main
memory, SRAM1 or the System memory. Refer to
configuration.
Bit 22 Not used
Bit 21 DUALBANK: Dual-Bank on 512 KB or 256 KB Flash memory devices
0: 256 KB/512 KB Single-bank Flash: Contiguous addresses in Bank 1
1: 256 KB/512 KB Dual-bank Flash: Refer to
Bit 20 BFB2: Dual-bank boot
0: Dual-bank boot disable
1: Dual-bank boot enable
Bit 19 WWDG_SW: Window watchdog selection
0: Hardware window watchdog
1: Software window watchdog
DocID024597 Rev 3
[47:40] [39:32] 31
PCROP2_STRT
PCROP2_END
WRP2A
Unused Unused
_STRT
WRP2B
Unused Unused
_STRT
24 23 22
SRAM2
n
Res.
BOOT1
_PE
r r
8 7 6
r r r
Embedded Flash memory (FLASH)
[30:24] [23:16] [15:8]
Unused
Unused PCROP2_STRT
Unused
WRP2A
Unused
_END
WRP2B
Unused
_END
21 20 19 18
DUAL WWDG IWGD_
BFB2
BANK _SW STDBY
r r r
5 4 3 2
RDP[7:0]
r r r
Section 2.6: Boot
Table 6 and Table
[7:0]
PCROP2_END
WRP2A
_STRT
WRP2B
_STRT
17 16
IWDG_ IWDG_
StOP SW
r r r
1 0
r r r
7.
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