ST STM32L4x6 Reference Manual page 205

RM0351
Bits 14:8 PLLN[6:0]: Main PLL multiplication factor for VCO
Caution:
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 PLLM: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
Caution:
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 PLLSRC: Main PLL, PLLSAI1 and PLLSAI2 entry clock source
Set and cleared by software to control the multiplication factor of the VCO. These bits can be
written only when the PLL is disabled.
VCO output frequency = VCO input frequency x PLLN with 8 =< PLLN =< 86
0000000: PLLN = 0 wrong configuration
0000001: PLLN = 1 wrong configuration
...
0000111: PLLN = 7 wrong configuration
0001000: PLLN = 8
0001001: PLLN = 9
...
1010101: PLLN = 85
1010110: PLLN = 86
1010111: PLLN = 87 wrong configuration
...
1111111: PLLN = 127 wrong configuration
The software has to set correctly these bits to assure that the VCO output
frequency is between 64 and 344 MHz.
Set and cleared by software to divide the PLL, PLLSAI1 and PLLSAI2 input clock before the
VCO. These bits can be written only when all PLLs are disabled.
VCO input frequency = PLL input clock frequency / PLLM with 1 <= PLLM <= 8
000: PLLM = 1
001: PLLM = 2
010: PLLM = 3
011: PLLM = 4
100: PLLM = 5
101: PLLM = 6
110: PLLM = 7
111: PLLM = 8
The software has to set these bits correctly to ensure that the VCO input
frequency ranges from 4 to 16 MHz.
Set and cleared by software to select PLL, PLLSAI1 and PLLSAI2 clock source. These bits
can be written only when PLL, PLLSAI1 and PLLSAI2 are disabled.
In order to save power, when no PLL is used, the value of PLLSRC should be 00.
00: No clock sent to PLL, PLLSAI1 and PLLSAI2
01: MSI clock selected as PLL, PLLSAI1 and PLLSAI2 clock entry
10: HSI16 clock selected as PLL, PLLSAI1 and PLLSAI2 clock entry
11: HSE clock selected as PLL, PLLSAI1 and PLLSAI2 clock entry
DocID024597 Rev 3
Reset and clock control (RCC)
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