Figure 151. Dfsdm_Chdatinyr Registers Operation Modes And Assignment; Channel Selection - ST STM32L4x6 Reference Manual

Digital filter for sigma delta modulators (DFSDM)

Figure 151. DFSDM_CHDATINyR registers operation modes and assignment

The write into DFSDM_CHDATINyR register to load one or two samples must be performed
after the selected input channel (channel y) is enabled for data collection (starting
conversion for channel y). Otherwise written data are lost for next processing.
For example: for single conversion and interleaved mode, do not start writing pair of data
samples into DFSDM_CHDATINyR before the single conversion is started (any data
present in the DFSDM_CHDATINyR before starting a conversion is discarded).
21.3.7

Channel selection

There are 8 multiplexed channels which can be selected for conversion using the injected
channel group and/or using the regular channel.
The injected channel group is a selection of any or all of the 8 channels. JCHG[7:0] in the
DFSDMx_JCHGR register selects the channels of the injected group, where JCHG[y]=1
means that channel y is selected.
Injected conversions can operate in scan mode (JSCAN=1) or single mode (JSCAN=0). In
scan mode, each of the selected channels is converted, one after another. The lowest
channel (channel 0, if selected) is converted first, followed immediately by the next higher
channel until all the channels selected by JCHG[7:0] have been converted. In single mode
(JSCAN=0), only one channel from the selected channels is converted, and the channel
selection is moved to the next channel. Writing to JCHG[7:0] if JSCAN=0 resets the channel
selection to the lowest selected channel.
Injected conversions can be launched by software or by a trigger. They are never
interrupted by regular conversions.
The regular channel is a selection of just one of the 8 channels. RCH[2:0] in the
DFSDMx_CR1 register indicates the selected channel.
Regular conversions can be launched only by software (not by a trigger). A sequence of
continuous regular conversions is temporarily interrupted when an injected conversion is
requested.
Performing a conversion on a disabled channel (CHEN=0 in DFSDM_CHCFGyR1 register)
causes that the conversion will never end - because no input data is provided (with no clock
signal). In this case, it is necessary to enable a given channel (CHEN=1 in
DFSDM_CHCFGyR1 register) or to stop the conversion by DFEN=0 in DFSDMx_CR1
register.
618/1693 DocID024597 Rev 3
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