Figure 339. Control Circuit In Normal Mode, Internal Clock Divided By 1; Debug Mode - ST STM32L4x6 Reference Manual

RM0351

Figure 339. Control circuit in normal mode, internal clock divided by 1

29.3.5

Debug mode

When the microcontroller enters the debug mode (Cortex
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module. For more details, refer to
support for timers, RTC, watchdog, bxCAN and
29.4 TIM6/TIM7 registers
Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
29.4.1 TIM6/TIM7 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15 14 13
Res Res Res
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 UIFREMAP: UIF status bit remapping
Bits 10:8 Reserved, must be kept at reset value.
Section 1.1 on page 61
12 11 10 9
UIF
Res RE- Res Res
MAP
rw
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
I2C.
for a list of abbreviations used in register descriptions.
8 7 6
Res ARPE Res
rw
DocID024597 Rev 3
Basic timers (TIM6/TIM7)
®
-M4 core - halted), the TIMx
Section 44.16.2: Debug
5 4 3 2
Res Res OPM URS
rw rw
1 0
UDIS CEN
rw rw
1017/1693
1022