Flash Option Register (Flash_Optr) - ST STM32L4x6 Reference Manual

RM0351
Bits 23:21 Reserved, must be kept at reset value.
Bits 18:0 ADDR_ECC: ECC fail address
3.7.8

Flash option register (FLASH_OPTR)

Address offset: 0x20
Reset value: 0xFXXX XXXX. The option bits are loaded with values from Flash memory at
reset release.
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
31 30 29
Res. Res. Res. Res.
15 14 13
nRST_ nRST_ nRST_
Res.
SHDW STDBY STOP
rw rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 24 ECCIE: ECC correction interrupt enable
0: ECCC interrupt disabled
1: ECCC interrupt enabled
Bit 20 SYSF_ECC: System Flash ECC fail
This bit indicates that the ECC error correction or double ECC error detection is
located in the System Flash.
Bit 19 BK_ECC: ECC fail bank
This bit indicates which bank is concerned by the ECC error correction or by the
double ECC error detection.
0: bank 1
1: bank 2
This bit indicates which address in the bank is concerned by the ECC error
correction or by the double ECC error detection.
28 27 26 25
SRAM2
Res. Res.
_RST
rw
12 11 10 9
Res. BOR_LEV[2:0]
rw rw rw
Bit 25 SRAM2_RST: SRAM2 Erase when system reset
0: SRAM2 erased when a system reset occurs
1: SRAM2 is not erased when a system reset occurs
Bit 24 SRAM2_PE: SRAM2 parity check enable
0: SRAM2 parity check enable
1: SRAM2 parity check disable
Bit 23 nBOOT1: Boot configuration
Together with the BOOT0 pin, this bit selects boot mode from the Flash main
memory, SRAM1 or the System memory. Refer to
configuration.
Bit 22 Reserved, must be kept at reset value.
DocID024597 Rev 3
Embedded Flash memory (FLASH)
24 23 22
SRAM2 nBOOT DUAL
Res.
_PE 1 BANK
rw rw
8 7 6
rw rw rw
21 20 19 18
WWDG IWGD_
BFB2
_SW STDBY
rw rw rw rw
5 4 3 2
RDP[7:0]
rw rw rw rw
Section 2.6: Boot
17 16
IWDG_
IWDG_
SW
StOP
rw rw
1 0
rw rw
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