Control/Status Register (Rcc_Csr) - ST STM32L4x6 Reference Manual

Reset and clock control (RCC)
6.4.30

Control/status register (RCC_CSR)

Address: 0x94
Reset value: 0x0C00 0600, reset by system Reset, except reset flags by power Reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
31 30 29
LPWR WWDG IWWG
RSTF RSTF RSTF RSTF
r r r
15 14 13
Res. Res. Res.
Bit 31 LPWRRSTF: Low-power reset flag
Bit 30 WWDGRSTF: Window watchdog reset flag
Bit 29 IWDGRSTF: Independent window watchdog reset flag
Bit 28 SFTRSTF: Software reset flag
Bit 27 BORRSTF: BOR flag
Bit 26 PINRSTF: Pin reset flag
248/1693
28 27 26 25
SFT BOR PIN OB L
RSTF RSTF RSTF
r r r r
12 11 10 9
Res. MSISRANGE[3:0]
rw rw rw
Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry.
Cleared by writing to the RMVF bit.
0: No illegal mode reset occurred
1: Illegal mode reset occurred
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Set by hardware when an independent watchdog reset domain occurs.
Cleared by writing to the RMVF bit.
0: No independent watchdog reset occurred
1: Independent watchdog reset occurred
Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Set by hardware when a BOR occurs.
Cleared by writing to the RMVF bit.
0: No BOR occurred
1: BOR occurred
Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
24 23 22
FW
RMVF Res.
RSTF
r rw
8 7 6
Res. Res.
rw
DocID024597 Rev 3
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
RM0351
17 16
Res. Res.
1 0
LSI
LSION
RDY
r rw