ST STM32L4x6 Reference Manual page 214

Reset and clock control (RCC)
Bit 3 HSIRDYF: HSI16 ready interrupt flag
Bit 2 MSIRDYF: MSI ready interrupt flag
Bit 1 LSERDYF: LSE ready interrupt flag
Bit 0 LSIRDYF: LSI ready interrupt flag
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Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a
response to setting the HSION (refer to
not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit
is not set and no interrupt is generated.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI16 oscillator
1: Clock ready interrupt caused by the HSI16 oscillator
Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set.
Cleared by software setting the MSIRDYC bit.
0: No clock ready interrupt caused by the MSI oscillator
1: Clock ready interrupt caused by the MSI oscillator
Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
DocID024597 Rev 3
Clock control register (RCC_CR)). When HSION is
RM0351