Table 128. Example Of Frame Rate Calculation; Frequency Generator - ST STM32L4x6 Reference Manual

RM0351
22.3.2

Frequency generator

This clock source must be stable in order to obtain accurate LCD timing and hence
minimize DC voltage offset across LCD segments. The input clock LCDCLK can be divided
by any value from 1 to 2
on page
16 to 31 clock divider. The PS[3:0] bits, in the LCD_FCR register, select LCDCLK divided by
PS[3:0]
2 . If a finer resolution rate is required, the DIV[3:0] bits, in the LCD_FCR register, can
be used to divide the clock further by 16 to 31. In this way you can roughly scale the
frequency, and then fine-tune it by linearly scaling the clock with the counter. The output of
the frequency generator block is f
controller. The ck_div frequency is equivalent to the LCD phase frequency, rather than the
frame frequency (they are equal only in case of static duty). The frame frequency (f
obtained from f
multiplying it for the duty). Thus the relation between the input clock frequency (f
the frequency generator and its output clock frequency f
This makes the frequency generator very flexible. An example of frame rate calculation is
shown in
LCDCLK
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
The frame frequency must be selected to be within a range of around ~30 Hz to ~100 Hz
and is a compromise between power consumption and the acceptable refresh rate. In
15
x 31 (see
682). The frequency generator consists of a prescaler (16-bit ripple counter) and a
by dividing it by the number of active common terminals (or by
ck_div
Table 128.

Table 128. Example of frame rate calculation

PS[3:0]
3
4
4
5
6
1
2
2
3
4
6
7
7
8
9
DocID024597 Rev 3
Liquid crystal display controller (LCD)
Section 22.6.2: LCD frame control register (LCD_FCR)
which constitutes the time base for the entire LCD
ck_div
f
LCDCLK
f
= ------------------------------------------------ -
ckdiv
PS
× 〈
2 16 DIV
+
×
f f duty
=
frame ckdiv
DIV[3:0] Ratio
1 136
1 272
6 352
1 544
1 1088
4 40
4 80
11 108
4 160
4 320
3 1216
3 2432
10 3328
3 4864
3 9728
is:
ck_div
〉
Duty
1/8
1/4
1/3
1/2
static
1/8
1/4
1/3
1/2
static
1/8
1/4
1/3
1/2
static
) is
frame
) of
LCDCLK
f
frame
30.12 Hz
30.12 Hz
31.03 Hz
30.12 Hz
30.12 Hz
102.40 Hz
102.40 Hz
101.14 Hz
102.40 Hz
102.40 Hz
102.80 Hz
102.80 Hz
100.16 Hz
102.80 Hz
102.80 Hz
661/1693
690