Tim8 Option Register 1 (Tim8_Or1) - ST STM32L4x6 Reference Manual

Advanced-control timers (TIM1/TIM8)
Bits 1:0 ETR_ADC1_RMP: External trigger remap on ADC1 analog watchdog
Note: ADC1 AWDx sources are 'ORed' with the TIM1_ETR input signals. When ADC1 AWDx
26.4.22

TIM8 option register 1 (TIM8_OR1)

Address offset: 0x50
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:5 Reserved, must be kept at reset value
Bit 4 TI1_RMP: Input Capture 1 remap
Bits 3:2 ETR_ADC3_RMP: External trigger remap on ADC3 analog watchdog
Note: ADC3 AWDx sources are 'ORed' with the TIM8_ETR input signals. When ADC3 AWDx
Bits 1:0 ETR_ADC2_RMP: External trigger remap on ADC1 analog watchdog
Note: ADC2 AWDx sources are 'ORed' with the TIM8_ETR input signals. When ADC2 AWDx
842/1693
00 : TIM1_ETR is not connected to ADC1 AWDx. This configuration must be selected when
the ETR comes from the I/O.
01 : TIM1_ETR is connected to ADC1 AWD1.
10 : TIM1_ETR is connected to ADC1 AWD2.
11 : TIM1_ETR is connected to ADC1 AWD3.
is used, it is necessary to make sure that the corresponding TIM1_ETR input pin is not
enabled in the alternate function controller. Refer to
circuitry.
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
0: TIM8 input capture 1 is connected to I/O
1: TIM8 input capture 1 is connected to COMP2 output.
00: TIM8_ETR is not connected to ADC3 AWDx. This configuration must be selected when
the ETR comes from the I/O.
01: TIM8_ETR is connected to ADC3 AWD1.
10: TIM8_ETR is connected to ADC3 AWD2.
11: TIM8_ETR is connected to ADC3 AWD3.
is used, it is necessary to make sure that the corresponding TIM8_ETR input pin is not
enabled in the alternate function controller. Refer to
circuitry.
00 : TIM8_ETR is not connected to ADC2 AWDx. This configuration must be selected when
the ETR comes from the I/O.
01 : TIM8_ETR is connected to ADC2 AWD1.
10 : TIM8_ETR is connected to ADC2 AWD2.
11 : TIM8_ETR is connected to ADC2 AWD3.
is used, it is necessary to make sure that the corresponding TIM8_ETR input pin is not
enabled in the alternate function controller. Refer to
circuitry.
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. Res. Res. Res.
DocID024597 Rev 3
Figure 210: TIM1 ETR input
20 19 18
Res. Res. Res.
4 3 2
TI1_
ETR_ADC3_RMP
RMP
rw rw rw
Figure 211: TIM8 ETR input
Figure 211: TIM8 ETR input
RM0351
17 16
Res. Res.
1 0
ETR_ADC2_RMP
rw rw