Stop 2 Mode; Table 25. Stop 1 Mode - ST STM32L4x6 Reference Manual

Power control (PWR)
Refer to
Stop 1 mode
Mode entry
Mode exit
Wakeup latency
5.3.8

Stop 2 mode

The Stop 2 mode is based on the Cortex
clock gating. In Stop 2 mode, all clocks in the V
the HSI16 and the HSE oscillators are disabled. Some peripherals with wakeup capability
(I2C3 and LPUART) can switch on the HSI16 to receive a frame, and switch off the HSI16
after receiving the frame if it is not a wakeup frame. In this case the HSI16 clock is
propagated only to the peripheral requesting it.
SRAM1, SRAM2 and register contents are preserved.
The BOR is always available in Stop 2 mode. The consumption is increased when
thresholds higher than V
Note: The comparators outputs, the LPUART outputs and the LPTIM1 outputs are forced to low
speed (OSPEEDy=00) during the Stop 2 mode.
154/1693
Table 25: Stop 1 mode
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP bit is set in Cortex
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = "001" in PWR_CR1
On Return from ISR while:
– SLEEPDEEP bit is set in Cortex
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = "001" in PWR_CR1
Note: To enter Stop 1 mode, all EXTI Line pending bits (in
register 1
interrupts must be cleared. Otherwise, the Stop 1 mode entry
procedure is ignored and program execution continues.
If WFI or Return from ISR was used for entry
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 42: STM32L4x6 vector
If WFE was used for entry and SEVONPEND = 0:
Any EXTI Line configured in event mode. Refer to
Wakeup event
If WFE was used for entry and SEVONPEND = 1:
Any EXTI Line configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer
toTable 42: STM32L4x6 vector
Wakeup event: refer to
Longest wakeup time between: MSI or HSI16 wakeup time and regulator
wakeup time from Low-power mode + Flash wakeup time from Stop 1
mode.
BOR0
for details on how to enter and exit Stop 1 mode.

Table 25. Stop 1 mode

(EXTI_PR1)), and the peripheral flags generating wakeup
management.
Section 12.3.2: Wakeup event management
®
-M4 deepsleep mode combined with peripheral
CORE
are used.
DocID024597 Rev 3
Description
®
-M4 System Control register
®
-M4 System Control register
table.
Section 12.3.2:
table.
domain are stopped, the PLL, the MSI,
RM0351
Pending