ST STM32L4x6 Reference Manual page 316

Direct memory access controller (DMA)
Bits 15:12 C4S[3:0]: DMA channel 4 selection
Bits 11:8 C3S[3:0]: DMA channel 3 selection
Bits 7:4 C2S[3:0]: DMA channel 2 selection
Bits 3:0 C1S[3:0]: DMA channel 1 selection
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0000: Channel 4 mapped on ADC2
0001: Channel 4 mapped on SAI2_B
0010: Reserved
0011: Channel 4 mapped on TIM6_UP/DAC1
0100: Channel 4 mapped on SPI1_TX
0101: Channel 4 mapped on TIM5_CH2
0110: Reserved
0111: Channel 4 mapped on SDMMC1
others: Reserved
0000: Channel 3 mapped on ADC1
0001: Channel 3 mapped on SAI2_A
0010: Channel 3 mapped on UART4_TX
0011: Reserved
0100: Channel 3 mapped on SPI1_RX
0101: Reserved
0110: Channel 3 mapped on AES_OUT
0111: Reserved
others: Reserved
0000: Reserved
0001: Channel 2 mapped on SAI1_B
0010: Channel 2 mapped on UART5_RX
0011: Channel 2 mapped on SPI3_TX
0100: Channel 2 mapped on SWPMI1_TX
0101: Channel 2 mapped on TIM5_CH3/TIM5_UP
0110: Channel 2 mapped on AES_OUT
0111: Channel 2 mapped on TIM8_CH4/TIM8_TRIG/TIM8_COM
others: Reserved
0000: Reserved
0001: Channel 1 mapped on SAI1_A
0010: Channel 1 mapped on UART5_TX
0011: Channel 1 mapped on SPI3_RX
0100: Channel 1 mapped on SWPMI1_RX
0101: Channel 1 mapped on TIM5_CH4/TIM5_TRIG/TIM5_COM
0110: Channel 1 mapped on AES_IN
0111: Channel 1 mapped on TIM8_CH3/TIM8_UP
others: Reserved
DocID024597 Rev 3
RM0351