Table 100. Adc Register Map And Reset Values For Each Adc; For Master Adc, 0X100 For Slave Adc) - ST STM32L4x6 Reference Manual

Analog-to-digital converters (ADC)
Table 100. ADC register map and reset values for each ADC (offset=0x000
Offset Register
ADCx_ISR
0x00
Reset value
ADCx_IER
0x04
Reset value
ADCx_CR
0x08
Reset value 0
ADCx_CFGR
0x0C
Reset value 1
ADCx_CFGR2
0x0C
Reset value
ADCx_SMPR1
0x14
Reset value
ADCx_SMPR2
0x18
Reset value
0x1C Reserved
ADCx_TR1
0x20
Reset value
ADCx_TR2
0x24
Reset value
ADCx_TR3
0x28
Reset value
0x2C Reserved
ADCx_SQR1
0x30
Reset value
ADCx_SQR2
0x34
Reset value
ADCx_SQR3
0x38
Reset value
ADCx_SQR4
0x3C
Reset value
ADCx_DR
0x40
Reset value
0x44-
Reserved
0x48
538/1693

for master ADC, 0x100 for slave ADC)

0 1 0
AWD1CH[4:0]
0 0 0 0 0 0 0 0 0
SMP9 SMP8 SMP7
[2:0] [2:0] [2:0]
0 0 0 0 0 0 0 0
SMP18 SMP17
[2:0] [2:0]
0 0 0 0 0
HT1[11:0]
1 1 1 1 1 1
1 1
1 1
SQ4[4:0]
0 0 0 0 0 0
SQ9[4:0]
0 0 0 0 0 0
SQ14[4:0]
0 0 0 0 0 0
DocID024597 Rev 3
DISCNUM
[2:0]
0 0 0 0 0 0 0
SMP6 SMP5 SMP4
[2:0] [2:0] [2:0]
0 0 0 0 0 0 0 0
SMP16 SMP15 SMP14
[2:0] [2:0] [2:0]
0 0 0 0 0 0 0 0
Res.
1 1 1 1 1 1
HT2[[7:0]
1 1 1 1 1 1
HT3[[7:0]
1 1 1 1 1 1
Res.
SQ3[4:0] SQ2[4:0]
0 0 0 0 0 0 0
SQ8[4:0] SQ7[4:0]
0 0 0 0 0 0 0
SQ13[4:0] SQ12[4:0]
0 0 0 0 0 0 0
0 0
Res.
0 0 0 0 0 0
0 0 0 0 0 0
0
EXTSEL
[3:0]
0 0 0 0 0 0 0 0 0
OVSS[3:0]
0 0 0 0 0 0
SMP3 SMP2
[2:0] [2:0]
0 0 0 0 0 0 0 0 0
SMP13 SMP12
[2:0] [2:0]
0 0 0 0 0 0 0 0 0
LT1[11:0]
0 0 0 0 0 0 0
0 0 0
0 0 0
SQ1[4:0]
0 0 0 0 0 0 0
SQ6[4:0]
0 0 0 0 0 0 0
SQ11[4:0]
0 0 0 0 0 0 0
SQ16[4:0]
0 0 0 0 0
regular RDATA[15:0]
0 0 0 0 0 0 0 0 0
RM0351
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
RES
[1:0]
0 0 0 0
OVSR
[2:0]
0 0 0 0 0
SMP1 SMP0
[2:0] [2:0]
0 0 0 0 0
SMP11 SMP10
[2:0] [2:0]
0 0 0 0 0
0 0 0 0 0
LT2[7:0]
0 0 0 0 0
LT3[7:0]
0 0 0 0 0
L[3:0]
0 0 0 0
SQ5[4:0]
0 0 0 0 0
SQ10[4:0]
0 0 0 0 0
SQ15[4:0]
0 0 0 0 0
0 0 0 0 0