RM0351
Bits 12:9 TCLR[3:0]: CLE to RE delay.
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 8:7 Reserved, must be kept at reset value
Bit 6 ECCEN: ECC computation logic enable bit
Bits 5:4 PWID[1:0]: Data bus width.
Bit 3 PTYP: Memory type.
Bit 2 PBKEN: NAND Flash memory bank enable bit.
Bit 1 PWAITEN: Wait feature enable bit.
Bit 0 Reserved, must be kept at reset value
FIFO status and interrupt register (FMC_SR)
Address offset: 0x84
Reset value: 0x0000 0040
This register contains information about the FIFO status and interrupt. The FMC features a
FIFO that is used when writing to memories to transfer up to 16 words of data from the AHB.
This is used to quickly write to the FIFO and free the AHB for transactions to peripherals
other than the FMC, while the FMC is draining its FIFO into the memory. One of these
register bits indicates the status of the FIFO, for ECC purposes.
The ECC is calculated while the data are written to the memory. To read the correct ECC,
the software must consequently wait until the FIFO is empty.
31
30
29
Res.
Res.
Res.
Res.
Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
0: ECC logic is disabled and reset (default after reset),
1: ECC logic is enabled.
Defines the external memory device width.
00: 8 bits
01: 16 bits (default after reset).
10: reserved.
11: reserved.
Defines the type of device attached to the corresponding memory bank:
0: Reserved, must be kept at reset value
1: NAND Flash (default after reset)
Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB
bus
0: Corresponding memory bank is disabled (default after reset)
1: Corresponding memory bank is enabled
Enables the Wait feature for the NAND Flash memory bank:
0: disabled
1: enabled
28
27
26
25
Res.
Res.
Res.
Flexible static memory controller (FSMC)
24
23
22
Res.
Res.
Res.
DocID024597 Rev 3
21
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19
18
Res.
Res.
Res.
Res.
17
16
Res.
Res.
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