Table 41. Dma Register Map And Reset Values - ST STM32L4x6 Reference Manual

RM0351
10.5.9 DMA register map
The following table gives the DMA register map and the reset values.
Offset Register
DMA_ISR
0x00
Reset value
DMA_IFCR
0x04
Reset value
DMA_CCR1
0x08
Reset value
DMA_CNDTR1
0x0C
Reset value
DMA_CPAR1
0x10
Reset value 0
DMA_CMAR1
0x14
Reset value 0
DMA_CCR2
0x1C
Reset value
DMA_CNDTR2
0x20
Reset value
DMA_CPAR2
0x24
Reset value 0
DMA_CMAR2
0x28
Reset value 0
DMA_CCR3
0x30
Reset value
DMA_CNDTR3
0x34
Reset value
DMA_CPAR3
0x38
Reset value 0
DMA_CMAR3
0x3C
Reset value 0
DMA_CCR4
0x44
Reset value
DMA_CNDTR4
0x48
Reset value

Table 41. DMA register map and reset values

0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
DocID024597 Rev 3
Direct memory access controller (DMA)
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0
0 0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
0 0
0 0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
0 0
0 0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
0 0
0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PL
[1:0]
0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PL
[1:0]
0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PL
[1:0]
0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PL
[1:0]
0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
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