Flash Bank 1 Pcrop End Address Register (Flash_Pcrop1Er); Flash Bank 1 Wrp Area A Address Register (Flash_Wrp1Ar) - ST STM32L4x6 Reference Manual

RM0351
Access: no wait state when no Flash memory operation is on going, word, half-word access
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept cleared
3.7.10

Flash Bank 1 PCROP End address register (FLASH_PCROP1ER)

Address offset: 0x28
Reset value: 0xX000 XXXX
Access: no wait state when no Flash memory operation is on going, word, half-word access.
PCROP_RDP bit can be accessed with byte access
31 30 29
PCROP
Res. Res.
_RDP
rs
15 14 13
rw rw rw
Bits 30:16 Reserved, must be kept cleared
3.7.11

Flash Bank 1 WRP area A address register (FLASH_WRP1AR)

Address offset: 0x2C
Reset value: 0x00XX 00XX
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
Bits 15:0 PCROP1_STRT: Bank 1 PCROP area start offset
PCROP1_STRT contains the first double-word of the PCROP area.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
rw rw rw rw
Bit 31 PCROP_RDP: PCROP area preserved when RDP level decreased
This bit is set only. It is reset after a full mass erase due to a change of RDP
from Level 1 to Level 0.
0: PCROP area is not erased when the RDP level is decreased from Level 1 to
Level 0.
1: PCROP area is erased when the RDP level is decreased from Level 1 to
Level 0 (full mass erase).
Bits 15:0 PCROP1_END: Bank 1 PCROP area end offset
PCROP1_END contains the last double-word of the bank 1 PCROP area.
24 23 22
Res. Res. Res.
8 7 6
PCROP1_STRT[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
PCROP1_END[15:0]
rw rw rw
DocID024597 Rev 3
Embedded Flash memory (FLASH)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
17 16
Res. Res.
1 0
rw rw
17 16
Res. Res.
1 0
rw rw
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