ST STM32L011 3 Series Errata Sheet
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ST STM32L011 3 Series Errata Sheet

ST STM32L011 3 Series Errata Sheet

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Applicability
This document applies to the part numbers of STM32L011xx/L021xx devices and the device variants as stated in this page.
It gives a summary and a description of the device errata, with respect to the device datasheet and reference manual RM0377.
Deviation of the real device behavior from the intended device behavior is considered to be a device limitation. Deviation of the
description in the reference manual or the datasheet from the intended device behavior is considered to be a documentation
erratum. The term "errata" applies both to limitations and documentation errata.
Reference
STM32L011x3/4
STM32L021x4
Reference
STM32L011x3/4
STM32L021x4
1. Refer to the device datasheet for how to identify this code on different types of package.
2. REV_ID[15:0] bitfield of DBG_IDCODE register.
ES0332 - Rev 5 - February 2022
For further information contact your local STMicroelectronics sales office.
Table 1.
Device summary
STM32L011K4, STM32L011K3, STM32L011G4, STM32L011G3, STM32L011F4, STM32L011F3,
STM32L011E4, STM32L011E3, STM32L011D4, STM32L011D3
STM32L021K4, STM32L021G4, STM32L021F4, STM32L021D4
Table 2.
Device variants
Device marking
A
1, Z
STM32L011x3/4 STM32L021x3/4
STM32L011xx/L021xx device errata
Part numbers
Silicon revision codes
(1)
Errata sheet
(2)
REV_ID
0x1000
0x1008
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  • Page 1 1. Refer to the device datasheet for how to identify this code on different types of package. 2. REV_ID[15:0] bitfield of DBG_IDCODE register. ES0332 - Rev 5 - February 2022 www.st.com For further information contact your local STMicroelectronics sales office.

  • Page 2: Summary Of Device Errata

    STM32L011x3/4 STM32L021x3/4 Summary of device errata Summary of device errata The following table gives a quick reference to the STM32L011xx/L021xx device limitations and their status: A = limitation present, workaround available N = limitation present, no workaround available P = limitation present, partial workaround available “-”...
  • Page 3 STM32L011x3/4 STM32L021x3/4 Summary of device errata Status Function Section Limitation Rev. Rev. 1, Z 2.9.4 Spurious bus error detection in master mode 2.9.5 Last-received byte loss in reload mode 2.9.6 Spurious master transfer upon own slave address match 2.9.8 OVR flag not set in underrun condition 2.9.9 Transmission stalled after first byte transfer 2.10.1...

  • Page 4: Description Of Device Errata

    STM32L011x3/4 STM32L021x3/4 Description of device errata Description of device errata ® The following sections describe limitations of the applicable devices with Arm core and provide workarounds if available. They are grouped by device functions. Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. System 2.1.1 Delay after an RCC peripheral clock enabling...

  • Page 5: Boot_Mode Bits Do Not Reflect The Selected Boot Mode

    (by setting the CGIFx bit of the DMA_IFCR register), the automatic channel disable fails and the TEIFx flag is not raised. This issue does not occur with ST's HAL software that does not use and clear the GIFx flag when the channel is active.

  • Page 6: Adc

    STM32L011x3/4 STM32L021x3/4 Workaround No application workaround is required. 2.3.1 Overrun flag is not set if EOC reset coincides with new conversion end Description If the EOC flag is cleared by an ADC_DR register read operation or by software during the same APB cycle in which the data from a new conversion are written in the ADC_DR register, the overrun event duly occurs (which results in the loss of either current or new data) but the overrun flag (OVR) may stay low.

  • Page 7: Tim

    STM32L011x3/4 STM32L021x3/4 Workaround None. For security reasons, it is recommended to avoid using SYSCFGRST bit of RCC_APB2RSTR when COMP1LOCK and/or COMP2LOCK bits are set. 2.5.1 PWM re-enabled in automatic output enable mode despite of system break Description In automatic output enable mode (AOE bit set in TIMx_BDTR register), the break input can be used to do a cycle-by-cycle PWM control for a current mode regulation.

  • Page 8: Output Compare Clear Not Working With External Counter Reset

    STM32L011x3/4 STM32L021x3/4 LPTIM • in center-aligned mode while up-counting, from ARR-1 to ARR (possibly a new ARR value if the period is also changed) at the crest (that is, when TIMx_RCR = 0): – first compare event: CNT = CCR = (ARR-1) –...

  • Page 9: Device May Remain Stuck In Lptim Interrupt When Clearing Event Flag

    STM32L011x3/4 STM32L021x3/4 LPTIM 2.6.2 Device may remain stuck in LPTIM interrupt when clearing event flag Description This limitation occurs when the LPTIM is configured in interrupt mode (at least one interrupt is enabled) and the software clears any flag in LPTIM_ISR register by writing its corresponding bit in LPTIM_ICR register. If the interrupt status flag corresponding to a disabled interrupt is cleared simultaneously with a new event detection, the set and clear commands might reach the APB domain at the same time, leading to an asynchronous interrupt signal permanently stuck high.

  • Page 10: Iwdg

    STM32L011x3/4 STM32L021x3/4 IWDG IWDG 2.7.1 IWDG does not always reset the device Description The IWDG must be configured so that the counter starts counting down and generates a reset when the end of count value is reached. In some cases, the configuration does not work: the IWDG remains stopped and does not reset the device.

  • Page 11: Calendar Initialization May Fail In Case Of Consecutive Init Mode Entry

    STM32L011x3/4 STM32L021x3/4 RTC and TAMP Figure 1. Masked RTC interrupt Failure window: Alarm A Flag is being set after the software checks its value Alarm A Flag does not raise EXTI flag because this one is not yet hardware cleared. Alarm B Flag Alarm A Flag EXTI Flag...

  • Page 12: Alarm Flag May Be Repeatedly Set When The Core Is Stopped In Debug

    STM32L011x3/4 STM32L021x3/4 Note: It is recommended to write all registers in a single initialization session to avoid accumulating synchronization delays. 2.8.4 Alarm flag may be repeatedly set when the core is stopped in debug Description When the core is stopped in debug mode, the clock is supplied to subsecond RTC alarm downcounter even though the device is configured to stop the RTC in debug.

  • Page 13: Wrong Behavior In Stop Mode

    STM32L011x3/4 STM32L021x3/4 2.9.2 Wrong behavior in Stop mode Description The correct use of the I2C peripheral is to disable it (PE = 0) before entering Stop mode, and re-enable it when back in Run mode. Some reference manual revisions may omit this information. Failure to respect the above while the MCU operating as slave or as master in multi-master topology enters Stop mode during a transfer ongoing on the I C-bus may lead to the following:...

  • Page 14: Last-Received Byte Loss In Reload Mode

    STM32L011x3/4 STM32L021x3/4 2.9.5 Last-received byte loss in reload mode Description If in master receiver mode or slave receive mode with SBC = 1 the following conditions are all met: • C-bus stretching is enabled (NOSTRETCH = 0) • RELOAD bit of the I2C_CR2 register is set •...

  • Page 15: Start Bit Is Cleared Upon Setting Addrcf, Not Upon Address Match

    STM32L011x3/4 STM32L021x3/4 The time for the software application to write the I2C_CR2 register before the Stop condition is limited, as the clock stretching (if enabled), is aborted when clearing the ADDR flag. Polling the BUSY flag before requesting the master transfer is not a reliable workaround as the bus may become busy between the BUSY flag check and the write into the I2C_CR2 register with the START bit set.

  • Page 16: Usart

    STM32L011x3/4 STM32L021x3/4 USART 2.10 USART 2.10.1 RTS is active while RE = 0 or UE = 0 Description The RTS line is driven low as soon as RTSE bit is set, even if the USART is disabled (UE = 0) or the receiver is disabled (RE = 0), that is, not ready to receive data.

  • Page 17: Spi

    STM32L011x3/4 STM32L021x3/4 2.12 2.12.1 BSY bit may stay high when SPI is disabled Description The BSY flag may remain high upon disabling the SPI while operating in: • master transmit mode and the TXE flag is low (data register full). •...

  • Page 18: Wrong Crc In Full-Duplex Mode Handled By Dma With Imbalanced Setting Of Data Counters

    STM32L011x3/4 STM32L021x3/4 A delay of up to two APB clock periods can be tolerated for the internal feedback delay. Main factors contributing to the delay increase are low VDD level, high temperature, high SCK pin capacitive load and low SCK I/O output speed. The SPI communication speed has no impact. The following table gives the maximum allowable APB frequency versus GPIOx_OSPEEDR output speed bitfield setting for the SCK pin, at 30pF of capacitive load.
  • Page 19 STM32L011x3/4 STM32L021x3/4 Workaround Apply one of the following measures: • Before transiting to master mode, hardware‑reset the SPI via the reset controller. • Set the MSTR and SPE bits of the SPI configuration register simultaneously, which forces the immediate start of the communication clock. In transmitter configuration, load the data register in advance with the data to send.

  • Page 20: Revision History

    STM32L011x3/4 STM32L021x3/4 Revision history Table 5. Document revision history Date Version Changes 30-Nov-2015 Initial release. Updated Section 2.1.5: NSS pin synchronization required when using bootloader with SPI1 interface on TSSOP14 package and extended to device revision Z. 02-Feb-2016 Added Section 2.2.1: Overrun flag might not be set when converted data have not been read before new data are written.

  • Page 21: Table Of Contents

    STM32L011x3/4 STM32L021x3/4 Contents Contents Summary of device errata............2 Description of device errata.
  • Page 22 STM32L011x3/4 STM32L021x3/4 Contents 2.8.5 Detection of a tamper event occurring before enabling the tamper detection is not supported in edge detection mode ......... . 12 I2C .
  • Page 23 ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’...

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