Apb1 Peripheral Clocks Enable In Sleep And Stop Modes Register - ST STM32L4x6 Reference Manual

RM0351
Bit 8 QSPISMEN Quad SPI memory interface clocks enable during Sleep and Stop modes
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCSMEN: Flexible memory controller clocks enable during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
6.4.25

APB1 peripheral clocks enable in Sleep and Stop modes register 1

(RCC_APB1SMENR1)
Address: 0x78
Reset value: 0xF2FE CA3FAccess: no wait state, word, half-word and byte access
31 30 29 28
LPTIM1 OPAMP DAC1 PWR
SMEN SMEN SMEN SMEN
rw rw rw rw
15 14 13 12
SPI3 SPI2
Res. Res.
SMEN SMEN
rw rw
Bit 31 LPTIM1SMEN: Low power timer 1 clocks enable during Sleep and Stop modes
Bit 30 OPAMPSMEN: OPAMP interface clocks enable during Sleep and Stop modes
Bit 29 DAC1SMEN: DAC1 interface clocks enable during Sleep and Stop modes
Bit 28 PWRSMEN: Power interface clocks enable during Sleep and Stop modes
Bits 27:26 Reserved, must be kept at reset value.
Set and cleared by software.
0: QUADSPI clocks disabled by the clock gating
1: QUADSPI clocks enabled by the clock gating
Set and cleared by software.
0: FMC clocks disabled by the clock gating
1: FMC clocks enabled by the clock gating
27 26 25
CAN1
Res. Res.
SMEN
rw
11 10 9
LCD
WWDG
Res.
SMEN SMEN
rw rw
Set and cleared by software.
0: LPTIM1 clocks disabled by the clock gating
1: LPTIM1 clocks enabled by the clock gating
Set and cleared by software.
0: OPAMP interface clocks disabled by the clock gating
1: OPAMP interface clocks enabled by the clock gating
Set and cleared by software.
0: DAC1 interface clocks disabled by the clock gating
1: DAC1 interface clocks enabled by the clock gating
Set and cleared by software.
0: Power interface clocks disabled by the clock gating
1: Power interface clocks enabled by the clock gating
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
24 23 22
I2C3 I2C2 I2C1
Res.
SMEN SMEN SMEN
rw rw
8 7 6
TIM7
Res. Res. Res.
SMEN
(1)
(1)
DocID024597 Rev 3
Reset and clock control (RCC)
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
21 20 19
UART5 UART4 USART3
SMEN SMEN SMEN
rw rw rw
5 4 3
TIM6 TIM5 TIM4
SMEN SMEN SMEN
rw rw rw
during Sleep and Stop modes
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
18 17 16
USART2
Res.
SMEN
rw rw
2 1 0
TIM3
TIM2
SMEN
SMEN
rw rw rw
237/1693
253