Dfsdm Extremes Detector Maximum Register (Dfsdmx_Exmax) - ST STM32L4x6 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 CLRAWHTF[7:0]: Clear the analog watchdog high threshold flag
CLRAWHTF[y]=0: Writing '0' has no effect
CLRAWHTF[y]=1: Writing '1' to position y clears the corresponding AWHTF[y] bit in the
DFSDMx_AWSR register
Bits 7:0 CLRAWLTF[7:0]: Clear the analog watchdog low threshold flag
CLRAWLTF[y]=0: Writing '0' has no effect
CLRAWLTF[y]=1: Writing '1' to position y clears the corresponding AWLTF[y] bit in the
DFSDMx_AWSR register
21.7.13

DFSDM Extremes detector maximum register (DFSDMx_EXMAX)

Address offset: 0x100 * (x+1) + 0x030, x = 0...3
Reset value: 0x8000 0000
31 30 29
r1 r0 r0
15 14 13
r0 r0 r0
Bits 31:8 EXMAX[23:0]: Extremes detector maximum value
These bits are set by hardware and indicate the highest value converted by DFSDM. EXMAX[23:0]
bits are reset to value (0x800000) by reading of this register.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 EXMAXCH[2:0]: Extremes detector maximum data channel.
These bits contains information about the channel on which the data is stored into EXMAX[23:0].
Bits are cleared by reading of this register.
21.7.14 DFSDM Extremes detector minimum register (DFSDMx_EXMIN)
Address offset: 0x100 * (x+1) + 0x034, x = 0...3Reset value: 0x7FFF FF00
31 30 29
r 0 r1 r1
15 14 13
r1 r1 r1
646/1693
28 27 26 25
r0 r0 r0 r0
12 11 10 9
EXMAX[7:0]
r0 r0 r0 r0
28 27 26 25
r1 r1 r1 r1
12 11 10 9
EXMIN[7:0]
r1 r1 r1 r1
DocID024597 Rev 3
24 23 22 21
EXMAX[23:8]
r0 r0 r0 r0
8 7 6 5
Res. Res. Res.
r0
24 23 22 21
EXMIN[23:8]
r1 r1 r1 r1
8 7 6 5
Res. Res. Res.
r1
20 19 18 17
r0 r0 r0 r0
4 3 2 1
Res. Res. EXMAXCH[2:0]
r r
20 19 18 17
r1 r1 r1 r1
4 3 2 1
Res. Res. EXMINCH[2:0]
r r
RM0351
16
r0
0
r
16
r1
0
r