S2: S-Bus; S3, S4: Dma-Bus; Busmatrix - ST STM32L4x6 Reference Manual

System and memory overview
2.1.3

S2: S-bus

This bus connects the system bus of the Cortex
used by the core to access data located in a peripheral or SRAM area. The targets of this
bus are the SRAM1, the AHB1 peripherals including the APB1 and APB2 peripherals, the
AHB2 peripherals and the external memories through the FMC or QUADSPI.
2.1.4

S3, S4: DMA-bus

This bus connects the AHB master interface of the DMA to the BusMatrix.The targets of this
bus are the SRAM1 and SRAM2, the AHB1 peripherals including the APB1 and APB2
peripherals, the AHB2 peripherals and the external memories through the FMC or
QUADSPI.
2.1.5

BusMatrix

The BusMatrix manages the access arbitration between Masters. The arbitration uses a
Round Robin algorithm. The BusMatrix is composed of five masters (CPU AHB, System
bus, DCode bus, ICode bus, DMA1 and DMA2 bus) and seven slaves (FLASH, SRAM1,
SRAM2, AHB1 (including APB1 and APB2), AHB2 and FMC/QUADSPI).
AHB/APB bridges
The two AHB/APB bridges provide full synchronous connections between the AHB and the
2 APB buses, allowing flexible selection of the peripheral frequency.
Refer to
address mapping of the peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM1/2 and
Flash memory interface). Before using a peripheral you have to enable its clock in the
RCC_AHBxENR and the RCC_APBxENR registers.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
64/1693
Section 2.2.2: Memory map and register boundary addresses on page 67
®
-M4 core to the BusMatrix. This bus is
DocID024597 Rev 3
RM0351
for the