ST STM32L4x6 Reference Manual page 635

RM0351
Bit 31 Reserved, must be kept at reset value.
Bit 30 AWFSEL: Analog watchdog fast mode select
0: Analog watchdog on data output value (after the digital filter). The comparison is done after offset
correction and shift
1: Analog watchdog on channel transceivers value (after watchdog filter)
Bit 29 FAST: Fast conversion mode selection for regular conversions
0: Fast conversion mode disabled
1: Fast conversion mode enabled
When converting a regular conversion in continuous mode, having enabled the fast mode causes
each conversion (except the first) to execute faster than in standard mode. This bit has no effect on
conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDMx_CR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [F
t = [F
if FAST=1 in continuous mode (except first conversion):
t = [F
in case if F
t = I
OSR
where: f
input data rate in case of parallel data input.
Bits 28:27 Reserved, must be kept at reset value.
Bits 26:24 RCH[2:0]: Regular channel selection
0: Channel 0 is selected as the regular channel
1: Channel 1 is selected as the regular channel
...
7: Channel 7 is selected as the regular channel
Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is
especially useful in continuous mode (when RCONT=1). It also affects regular conversions which
are pending (due to ongoing injected conversion).
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 RDMAEN: DMA channel enabled to read data for the regular conversion
0: The DMA channel is not enabled to read regular data
1: The DMA channel is enabled to read regular data
This bit can be modified only when DFEN=0 (DFSDMx_CR1).
Bit 20 Reserved, must be kept at reset value.
Bit 19 RSYNC: Launch regular conversion synchronously with DFSDM0
0: Do not launch a regular conversion synchronously wi th DFSDM0
1: Launch a regular conversion in this DFSDM at the very moment when a regular conversion is
launched in DFSDM0
This bit can be modified only when DFEN=0 (DFSDMx_CR1).
Bit 18 RCONT: Continuous mode selection for regular conversions
0: The regular channel is converted just once for each conversion request
1: The regular channel is converted repeatedly after each conversion request
Writing '0' to this bit while a continuous regular conversion is already in progress stops the
continuous mode immediately.
* (I -1 + F ) + F
OSR OSR ORD
* (I -1 + 4) + 2] / f
OSR OSR
* I ] / f
OSR OSR DFSDM_CKIN
= F [9:0]+1 = 1 (filter bypassed, active only integrator):
OSR OSR
/ f (... but CNVCNT=0)
DFSDM_CKIN
is the channel input clock frequency (on given channel DFSDM_CKINy pin) or
DFSDM_CKIN
Digital filter for sigma delta modulators (DFSDM)
] / f ..... for Sinc
ORD DFSDM_CKIN
..... for FastSinc filter
DFSDM_CKIN
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