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Using the Chrom-ART Accelerator™ to refresh an LCD-TFT
display on STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers
Introduction
The purpose of this application note is to highlight how to refresh an LCD-TFT display via
the FSMC interface using the Chrom-ART Accelerator™ on
STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers.
The STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers implement a Chrom-Art
Accelerator™ (DMA2D) that is a specialized DMA dedicated to image manipulation.
It can perform the following operations:
• Filling a part or the whole of a destination image with a specific color
• Copying a part or the whole of a source image into a part or the whole of a destination
image with a pixel format conversion
• Blending a part and/or two complete source images with a different pixel format and
copying the result into a part or the whole of a destination image with a different color
format.
On the STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers, the flexible static memory
controller (FSMC) is used to access the LCD-TFT display through a parallel interface.
This application note explains on:
• How to connect the LCD-TFT display to the FSMC interface
• How to configure the DMA2D for the LCD-TFT display refresh
• How to use the DMA2D byte reordering features to directly drive Intel 8080 displays.
To fully benefit from this application note, the user should be familiar with the STM32
Chrom-ART Accelerator™ (DMA2D) as described in the STM32L4x6 advanced Arm
based 32-bit MCUs reference manual (RM0351) and the STM32L4Rxxx/L4Sxxx advanced
®
Arm
-based 32-bit MCUs reference manual (RM0432) available from the
STMicroelectronics website www.st.com.
Type
Microcontrollers
October 2017
Table 1. Applicable products
Product lines and part numbers
STM32L496AE, STM32L496AG, STM32L496QE, STM32L496QG,
STM32L496RE, STM32L496RG, STM32L496VE, STM32L496VG,
STM32L496ZE, STM32L496ZG
STM32L4A6AG, STM32L4A6QG, STM32L4A6RG, STM32L4A6VG,
STM32L4A6ZG
STM32L4R5/S5 line, STM32L4R7/S7 line, STM32L4R9/S9 line
DocID029937 Rev 2
AN4943
Application note
®
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1/22
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Table of Contents
Related Manuals for ST STM32L496 Series
Summary of Contents for ST STM32L496 Series
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Page 1: Table 1. Applicable Products
Chrom-ART Accelerator™ (DMA2D) as described in the STM32L4x6 advanced Arm based 32-bit MCUs reference manual (RM0351) and the STM32L4Rxxx/L4Sxxx advanced ® -based 32-bit MCUs reference manual (RM0432) available from the STMicroelectronics website www.st.com. Table 1. Applicable products Type Product lines and part numbers... -
Page 2: Table Of Contents
Contents AN4943 Contents Reference documents ........5 Chrom-ART Accelerator™... - Page 3 AN4943 List of tables List of tables Table 1. Applicable products ............1 Table 2.
- Page 4 List of figures AN4943 List of figures Figure 1. Display application typical use case ......... . . 6 Figure 2.
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Page 5: Reference Documents
AN4943 Reference documents Reference documents The following documents are available on www.st.com. ® • STM32L4x6 advanced Arm -based 32-bit MCUs reference manual (RM0351) ® • STM32L4Rxxx/L4Sxxx advanced Arm -based 32-bit MCUs reference manual (RM0432) • Discovery kit with STM32L496AG MCU user manual (UM2160) •... -
Page 6: Chrom-Art Accelerator™ (Dma2D) Application Use Case Overview
Chrom-ART Accelerator™ (DMA2D) application use case overview AN4943 Chrom-ART Accelerator™ (DMA2D) application use case overview A typical application displaying an image into an LCD-TFT display is divided in 2 steps. • Step1: creation of the frame buffer content – The frame buffer is built by composing graphical primitives like icons, pictures and fonts –... -
Page 7: Lcd-Tft Display On Fsmc
AN4943 LCD-TFT display on FSMC The Chrom-ART Accelerator™ (DMA2D) can update the whole image on the display (full refresh) or only a part of it (partial refresh). The configuration of the Chrom-ART Accelerator™ (DMA2D) (full or partial refresh) is done by programming specific registers through the high level HAL library function as shown in Section 4: Chrom-ART Accelerator™... -
Page 8: Display Command Set (Dcs) Software Interface
LCD-TFT display on FSMC AN4943 A typical connection is showed in Figure 2 Figure 2. Display bus interface specification Display AGND Power block DGND Host RESX D/CX Interface block Interface block D[15:0], D[8:0] or [D[7:0] MSv44255V1 Display Command Set (DCS) software interface The LCD-TFT displays can be controlled through the physical interface (here the FSMC bus) using software commands according to the display command set (DCS) as defined in the MIPI alliance specification for DCS. -
Page 9: Controlling The D/Cx Signal With Stm32L496Xx/L4A6Xx/L4Rxxx/L4Sxxx Microcontrollers
AN4943 LCD-TFT display on FSMC Controlling the D/CX signal with STM32L496xx/L4A6xx/ L4Rxxx/L4Sxxx microcontrollers The D/CX signal of the DBI protocol is used to distinguish the commands (when D/CX = 0) from the data (when D/CX = 1) transfers. There are 2 ways to control the 'Data/Command control' (D/CX) signal: By using a dedicated GPIO: –... -
Page 10: Table 4. Minimum Usable Fsmc Address Bit Depending On Image Size (16 Bit Rgb565 Access)
LCD-TFT display on FSMC AN4943 Figure 4. Automatic control of LCD-TFT display data/command by FSMC interface LCD-TFT display FSMC_D[15:0] Data[15:0] FSMC_A[x] Data/command selection Other control signals MSv44237V1 1. ‘x’ as high as possible according Table For example, if the image buffer size is 240x240 pixels and the transfer is done using 16 bits in RGB565 mode (one pixel transferred per access to LCD), the number of accesses are 240x240 = 57600 accesses and the FSMC address increments from 0x0000 0000 to 0x0000 E0FF. -
Page 11: Chrom-Art Accelerator™ (Dma2D) Configuration In Stm32Cubel4
AN4943 Chrom-ART Accelerator™ (DMA2D) configuration in STM32CubeL4 Chrom-ART Accelerator™ (DMA2D) configuration in STM32CubeL4 LCD partial refresh An example configuring the DMA2D for an LCD partial refresh is provided in the STM32Cube examples: STM32Cube_FW_L4\Firmware\Projects\STM32L496G-Discovery\Examples\DMA2D\ DMA2D_MemToMemWithLCD. The code used to configure and start the DMA2D is shown below: /* Configure LCD before image display: set first pixel position and image size */ /* the position of the partial refreshed window is defined here. - Page 12 Chrom-ART Accelerator™ (DMA2D) configuration in STM32CubeL4 AN4943 Dma2dHandle.Init.ColorMode = DMA2D_OUTPUT_RGB565; /* Output color mode is RGB565: 16 bpp */ Dma2dHandle.Init.OutputOffset = 0x0; /* No offset in output */ Dma2dHandle.Init.RedBlueSwap = DMA2D_RB_REGULAR; /* No R&B swap for the output image */ Dma2dHandle.Init.AlphaInverted = DMA2D_REGULAR_ALPHA;...
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Page 13: New Dma2D Features To Support Intel 8080 Displays
AN4943 New DMA2D features to support Intel 8080 displays New DMA2D features to support Intel 8080 displays On the STM32 microcontrollers, the pixel data are stored in the frame buffer memory in little- endian format. This means that the least significant byte is stored at the lowest address and the most significant byte is stored at the highest address. -
Page 14: Figure 5. 24Bpp Over 16-Bit Interface Color Coding
New DMA2D features to support Intel 8080 displays AN4943 Figure 5. 24bpp over 16-bit interface color coding B0 [7] G1 [7] R0 [7] B0 [6] G1 [6] R0 [6] B0 [5] G1 [5] R0 [5] B0 [4] G1 [4] R0 [4] B0 [3] G1 [3] R0 [3]... -
Page 15: Figure 6. 16Bpp Over 8-Bit Interface Color Coding
AN4943 New DMA2D features to support Intel 8080 displays Figure 6. 16bpp over 8-bit interface color coding R1 [4] R0 [4] G0 [2] G1 [2] R1 [3] R0 [3] G0 [1] G1 [1] R1 [2] R0 [2] G0 [0] G1 [0] R0 [1] B0 [4] R1 [1]... -
Page 16: Dma2D Reordering Features
New DMA2D features to support Intel 8080 displays AN4943 DMA2D reordering features The DMA2D output FIFO bytes can be reordered to support the display frame buffer update through a parallel interface (FSMC) directly from the DMA2D. The user can do combination of reordering operations to get the right byte endianness aligned with the display color coding. -
Page 17: Dma2D Reordering Use Case Examples
AN4943 New DMA2D features to support Intel 8080 displays DMA2D reordering use case examples 5.3.1 24bpp/18bpp over 16-bit FSMC data bus interface In order to support 24bpp displays using the 8080 standard, two operations are required on the frame buffer data: •... -
Page 18: 24Bpp/18Bpp Over 8-Bit Fsmc Data Bus Interface
New DMA2D features to support Intel 8080 displays AN4943 5.3.2 24bpp/18bpp over 8-bit FSMC data bus interface The red and blue swaps are required to get the correct order of bytes for 24bpp displays using an 8-bit data bus. Figure 9 shows the red and blue swap operation done by the DMA2D allowing to have the good bytes order. -
Page 19: 16Bpp Over 8-Bit Fsmc Data Bus Interface
AN4943 New DMA2D features to support Intel 8080 displays 5.3.3 16bpp over 8-bit FSMC data bus interface In order to drive the 16bpp Intel 8080 display over an 8-bit interface, the MSB and LSB bytes of a half word must be swapped. Figure 10 shows how the swap operation allows having the good bytes order. -
Page 20: Conclusion
Conclusion AN4943 Conclusion This application note gives a guideline to easily transfer images to an LCD-TFT display via the FSMC interface using the Chrom-ART Accelerator™ (DMA2D) without using the CPU or the DMA resources. A focus is given to the correct control of the 'Data/command control' signal of the LCD-TFT display. -
Page 21: Revision History
AN4943 Revision history Revision history Table 6. Document revision history Date Revision Changes 27-Jan-2017 Initial release. Added STM32L4Rxxx/L4Sxxx devices in the whole document. 23-Oct-2017 Added Section 5: New DMA2D features to support Intel 8080 displays. DocID029937 Rev 2 21/22... - Page 22 ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
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