Timx Prescaler (Timx_Psc) - ST STM32L4x6 Reference Manual

RM0351
Bit 31 Value depends on IUFREMAP in TIMx_CR1.
If UIFREMAP = 0
If UIFREMAP = 1
Bits 30:16 CNT[30:16]: Most significant part counter value (on TIM2 and TIM5)
Bits 15:0 CNT[15:0]: Least significant part of counter value
27.4.11

TIMx prescaler (TIMx_PSC)

Address offset: 0x28
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
27.4.12 TIMx auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0xFFFF FFFF
31 30 29
rw rw rw
15 14 13
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Bits 31:16 ARR[31:16]: High auto-reload value (on TIM2 and TIM5)
Bits 15:0 ARR[15:0]: Low Auto-reload Prescaler value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the
and behavior.
The counter is blocked while the auto-reload value is null.
27.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
Address offset: 0x34
Reset value: 0x0000
31 30 29
rw rw rw
CNT[31]: Most significant bit of counter value (on TIM2 and TIM5)
Reserved on other timers
UIFCPY: UIF Copy
This bit is a read-only copy of the UIF bit of the TIMx_ISR register
12 11 10 9
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The counter clock frequency CK_CNT is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event.
28 27 26 25
ARR[31:16] (depending on timers)
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12 11 10 9
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Section 27.3.1: Time-base unit on page 859
28 27 26 25
CCR1[31:16] (depending on timers)
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General-purpose timers (TIM2/TIM3/TIM4/TIM5)
8 7 6
PSC[15:0]
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24 23 22
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8 7 6
ARR[15:0]
rw rw rw
24 23 22
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DocID024597 Rev 3
5 4 3 2
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/ (PSC[15:0] + 1).
CK_PSC
21 20 19 18
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5 4 3 2
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for more details about ARR update
21 20 19 18
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1 0
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17 16
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1 0
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17 16
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