Adc Watchdog Threshold Register 3 (Adcx_Tr3) - ST STM32L4x6 Reference Manual

RM0351
16.5.10

ADC watchdog threshold register 3 (ADCx_TR3)

Address offset: 0x28
Reset value: 0x00FF 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 3.
Refer to
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 LT3[7:0]: Analog watchdog 3 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 3.
This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data.
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Section 16.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
DocID024597 Rev 3
Analog-to-digital converters (ADC)
24 23 22 21
Res.
rw rw rw
8 7 6 5
Res.
rw rw rw
20 19 18 17
HT3[7:0]
rw rw rw rw
4 3 2 1
LT3[7:0]
rw rw rw rw
16
rw
0
rw
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