ST STM32L4x6 Reference Manual page 399

RM0351
Offset Register
FMC_BWTR2
0x10C
Reset value
FMC_BWTR3
0x114
Reset value
FMC_BWTR4
0x11C
Reset value
FMC_PCR
0x80
Reset value
FMC_SR
0x84
Reset value
FMC_PMEM
0x88
Reset value 1
FMC_PATT
0x8C
Reset value 1
FMC_ECCR
0x94
Reset value 0
Refer to
Table 81. FMC register map (continued)
0 0
0 0
ACCM
OD[1:0]
0 0
MEMHIZx[7:0]
1 1 1 1 1 0 0 1
ATTHIZ[7:0]
1 1 1 1 1 0 0 1
0 0 0 0 0 0 0 0
Section 2.2.2 on page 67
Flexible static memory controller (FSMC)
BUSTURN[3:0]
1 1 1 1 1
BUSTURN[3:0]
1 1 1 1 1
BUSTURN[3:0]
1 1 1 1 1
ECCPS
TAR[3:0]
[2:0]
0 0 0 0 0
MEMHOLDx[7:0]
1 1 1 1 1 0 0 1
ATTHOLD[7:0]
1 1 1 1 1 0 0 1
ECCx[31:0]
0 0 0 0 0 0 0 0
for the register boundary addresses.
DocID024597 Rev 3
DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
1 1 1 1 1 1 1 1
DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
1 1 1 1 1 1 1 1
DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
1 1 1 1 1 1 1 1
TCLR[3:0]
0 0 0 0 0 0
MEMWAITx[7:0]
1 1 1 1 1 0 0 1
ATTWAIT[7:0]
1 1 1 1 1 0 0 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1
PWID
[1:0]
0 0 1 1 0 0
1 0 0 0 0 0 0
MEMSETx[7:0]
1 1 1 1 1 0 0
ATTSET[7:0]
1 1 1 1 1 0 0
0 0 0 0 0 0 0
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