ST STM32L4x6 Reference Manual page 242

Reset and clock control (RCC)
Bit 14 USART1SMEN: USART1clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART1clocks disabled by the clock gating
1: USART1clocks enabled by the clock gating
Bit 13 TIM8SMEN: TIM8 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM8 timer clocks disabled by the clock gating
1: TIM8 timer clocks enabled by the clock gating
Bit 12 SPI1SMEN: SPI1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI1 clocks disabled by the clock gating during
1: SPI1 clocks enabled by the clock gating during
Bit 11 TIM1SMEN: TIM1 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM1 timer clocks disabled by the clock gating
1: TIM1P timer clocks enabled by the clock gating
Bit 10 SDMMC1SMEN: SDMMC clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SDMMC clocks disabled by the clock gating
1: SDMMC clocks enabled by the clock gating
Bits 9:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGSMEN: SYSCFG + COMP + VREFBUF clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SYSCFG + COMP + VREFBUF clocks disabled by the clock gating
Stop modes
1: SYSCFG + COMP + VREFBUF clocks enabled by the clock gating
Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
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during Sleep and Stop modes
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during Sleep and
during Sleep and