ST STM32L4x6 Reference Manual page 241

RM0351
6.4.27 APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR)
Address: 0x80
Reset value: 0x0167 7C01
Access: word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
USART
TIM8 SPI1
Res. 1
SMEN SMEN
SMEN
rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 DFSDMSMEN: DFSDM timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: DFSDM clocks disabled by the clock gating
1: DFSDM clocks enabled by the clock gating
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI2SMEN: SAI2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SAI2 clocks disabled by the clock gating
1: SAI2 clocks enabled by the clock gating
Bit 21 SAI1SMEN: SAI1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SAI1 clocks disabled by the clock gating
1: SAI1 clocks enabled by the clock gating
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TIM17SMEN: TIM17 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM17 timer clocks disabled by the clock gating
1: TIM17 timer clocks enabled by the clock gating
Bit 17 TIM16SMEN: TIM16 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM16 timer clocks disabled by the clock gating
1: TIM16 timer clocks enabled by the clock gating
Bit 16 TIM15SMEN: TIM15 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM15 timer clocks disabled by the clock gating
1: TIM15 timer clocks enabled by the clock gating
Bit 15 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
12 11 10 9
SDMMC
TIM1
1 Res.
SMEN
SMEN
rw rw rw
DocID024597 Rev 3
24 23 22
DFSDM SAI2 SAI1
Res.
SMEN SMEN SMEN
rw rw
8 7 6
Res. Res. Res. Res.
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
(1)
(1)
(1)
(1)
(1)
Reset and clock control (RCC)
21 20 19 18
TIM17
Res. Res.
SMEN
rw rw
5 4 3 2
Res. Res. Res.
during Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
17 16
TIM16 TIM15
SMEN SMEN
rw rw
1 0
SYS
Res. CFG
SMEN
rw
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