Internal Clock Sources Calibration Register (Rcc_Icscr) - ST STM32L4x6 Reference Manual

RM0351
Bit 0 MSION: MSI clock enable
This bit is set and cleared by software.
Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown
mode.
Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode.
Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop
modes, or in case of a failure of the HSE oscillator
Set by hardware when used directly or indirectly as system clock.
0: MSI oscillator OFF
1: MSI oscillator ON
6.4.2

Internal clock sources calibration register (RCC_ICSCR)

Address offset: 0x04
Reset value: 0x10XX 00XX where X is factory-programmed.
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res.
15 14 13
MSITRIM[7:0]
rw rw rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:24 HSITRIM[4:0]: HSI16 clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the HSI16.
The default value is 16, which, when added to the HSICAL value, should trim the HSI16 to
16 MHz ± 1 %.
Bits 23:16 HSICAL[7:0]: HSI16 clock calibration
These bits are initialized at startup with the factory-programmed HSI16 calibration trim value.
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim
value.
Bits 15:8 MSITRIM[7:0]: MSI clock trimming
These bits provide an additional user-programmable trimming value that is added to the
MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the MSI.
Bits 7:0 MSICAL[7:0]: MSI clock calibration
These bits are initialized at startup with the factory-programmed MSI calibration trim value.
When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim
value.
28 27 26 25
HSITRIM[4:0]
rw rw rw rw
12 11 10 9
rw rw rwr rw
DocID024597 Rev 3
24 23 22 21
rw r r r
8 7 6 5
rw r r r
Reset and clock control (RCC)
20 19 18
HSICAL[7:0]
r r r
4 3 2
MSICAL[7:0]
r r r
17 16
r r
1 0
r r
199/1693
253