Pending Register 1 (Exti_Pr1) - ST STM32L4x6 Reference Manual

Extended interrupts and events controller (EXTI)
12.5.6

Pending register 1 (EXTI_PR1)

Address offset: 0x14
Reset value: undefined
31 30 29
Res. Res. Res. Res.
15 14 13
PIF15 PIF14 PIF13 PIF12
rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:18 PIFx: Pending interrupt flag on line x (x = 22 to 18)
Bits 16:0 PIFx: Pending interrupt flag on line x (x = 16 to 0)
12.5.7 Interrupt mask register 2 (EXTI_IMR2)
Address offset: 0x20
Reset value: 0x0000 0087
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value
Note: The reset value for the direct lines (line 17, lines from 23 to 34, line 39) is set to '1' in order
to enable the interrupt by default.
332/1693
28 27 26 25
Res. Res. Res.
12 11 10 9
PIF11 PIF10 PIF9
rc_w1 rc_w1 rc_w1
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a '1' to the bit.
Bit 17 Reserved, must be kept at reset value.
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a '1' to the bit.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Bits 7:0 IMx: Interrupt mask on line x (x = 39 to 32)
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
24 23 22
Res. Res. PIF22
rc_w1
8 7 6
PIF8 PIF7 PIF6
rc_w1 rc_w1 rc_w1
24 23 22
Res. Res. Res.
8 7 6
Res. IM39 IM38
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DocID024597 Rev 3
21 20 19 18
PIF21 PIF20 PIF19 PIF18
rc_w1 rc_w1 rc_w1 rc_w1
5 4 3 2
PIF5 PIF4 PIF3 PIF2
rc_w1 rc_w1 rc_w1 rc_w1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
IM37 IM36 IM35 IM34
rw rw rw rw
RM0351
17 16
Res. PIF16
rc_w1
1 0
PIF1 PIF0
rc_w1 rc_w1
17 16
Res. Res.
1 0
IM33 IM32
rw rw