Tim15 Capture/Compare Register 2 (Tim15_Ccr2) - ST STM32L4x6 Reference Manual

RM0351
28.5.14

TIM15 capture/compare register 2 (TIM15_CCR2)

Address offset: 0x38
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 CCR2[15:0]: Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
28.5.15 TIM15 break and dead-time register (TIM15_BDTR)
Address offset: 0x44
Reset value: 0x0000 0000
31 30 29
Res Res Res
15 14 13
MOE AOE BKP BKE
rw rw rw
Note: As the AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on
the LOCK configuration, it may be necessary to configure all of them during the first write
access to the TIMx_BDTR register.
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by
software or automatically depending on the AOE bit. It is acting only on the channels which are
configured in output.
0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register)
See OC/OCN enable description for more details
enable register (TIM15_CCER) on page
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
12 11 10 9
rw rw rw rw
28 27 26 25
Res Res Res Res
12 11 10 9
OSSR OSSI LOCK[1:0]
rw rw rw rw
in TIMx_BDTR register).
General-purpose timers (TIM15/16/17)
8 7 6
CCR2[15:0]
rw rw rw
24 23 22
Res Res Res
8 7 6
rw rw rw
976).
DocID024597 Rev 3
5 4 3
rw rw rw
21 20 19
Res Res Res Res
5 4 3
DTG[7:0]
rw rw rw
(Section 28.5.8: TIM15 capture/compare
2 1 0
rw rw rw
18 17 16
Res Res
2 1 0
rw rw rw
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