Dfsdmx Module Registers (X=0..3) - ST STM32L4x6 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
Bits 31:16 INDAT0[15:0]: Input data for channel y or channel y+1
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2).
If DATPACK[1:0]=0 (standard mode)
INDAT0[15:0] is write protected (not used for input sample).
If DATPACK[1:0]=1 (interleaved mode)
Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored
into INDAT0[15:0]. Both samples are read sequentially by DFSDM filter as two channel y data
samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of
channel (y+1).
For odd y channels: INDAT1[15:0] is write protected.
See Section 21.3.6: Parallel data inputs
INDAT0[15:1] is in the16-bit signed format.
Bits 15:0 INDAT0[15:0]: Input data for channel y
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2).
If DATPACK[1:0]=0 (standard mode)
Channel y data sample is stored into INDAT0[15:0].
If DATPACK[1:0]=1 (interleaved mode)
First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored
into INDAT1[15:0]. Both samples are read sequentially by DFSDM filter as two channel y data
samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: Channel y data sample is stored into INDAT0[15:0].
For odd y channels: INDAT0[15:0] is write protected.
See Section 21.3.6: Parallel data inputs
INDAT0[15:0] is in the16-bit signed format.
21.7

DFSDMx module registers (x=0..3)

21.7.1 DFSDM control register 1 (DFSDMx_CR1)
Address offset: 0x100 * (x+1), x = 0...3
Reset value: 0x0000 0000
31 30 29
AWF
Res. FAST Res.
SEL
rw rw
15 14 13
Res. JEXTEN[1:0] Res.
rw rw
634/1693
28 27 26 25
Res. RCH[2:0]
rw rw
12 11 10 9
Res. JEXTSEL[2:0]
rw rw
DocID024597 Rev 3
for more details.
for more details.
24 23 22 21
RDMA
Res. Res.
EN
rw rw
8 7 6 5
JDMA
Res. Res.
EN
rw rw
20 19 18 17
RCON RSW
Res. RSYNC
T START
rw rw r0w
4 3 2
JSW
JSCAN JSYNC Res.
START
rw rw r0w
RM0351
16
Res.
1 0
DFEN
rw