Tim1/Tim8 Capture/Compare Register 6 (Timx_Ccr6) - ST STM32L4x6 Reference Manual

RM0351
26.4.25

TIM1/TIM8 capture/compare register 6 (TIMx_CCR6)

Address offset: 0x5C
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 CCR6[15:0]: Capture/Compare 6 value
CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit
OC6PE). Else the preload value is copied in the active capture/compare 6 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC6 output.
26.4.26 TIM1 option register 2 (TIM1_OR2)
Address offset: 0x60
Reset value: 0x0000 0001
31 30 29
Res. Res. Res. Res.
15 14 13
ETRSEL[1:0] Res. Res.
rw rw
Bits 31:17 Reserved, must be kept at reset value
Bits 16:14 ETRSEL[2:0]: ETR source selection
This bit selects the ETR input source.
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
Bits 13:12 Reserved, must be kept at reset value
Bit 11 BKCMP2P: BRK COMP2 input polarity
This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP
polarity bit.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
12 11 10 9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
BK BK
BKINP
CMP2P CMP1P
rw rw rw
000: ETR legacy mode
001: COMP1 output connected to ETR input
010: COMP2 output connected to ETR input
Other codes reserved
bits in TIMx_BDTR register).
0: COMP2 input is active high
1: COMP2 input is active low
bits in TIMx_BDTR register).
8 7 6
CCR6[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
BKDFB
Res. Res.
K0E
rw
DocID024597 Rev 3
Advanced-control timers (TIM1/TIM8)
5 4 3
rw rw rw
21 20 19
Res. Res. Res.
5 4 3
Res. Res. Res.
CMP2E
2 1 0
rw rw rw
18 17 16
ETR
Res. Res. SEL
[2]
rw
2 1 0
BK BK
BKINE
CMP1E
rw rw rw
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