Read-While-Write (Rww) - ST STM32L4x6 Reference Manual

Embedded Flash memory (FLASH)
In fast programming: FASTERR is set if one of the following conditions occurs:
–
–
If an error occurs during a program or erase operation, one of the following error flags is set
in the FLASH_SR register:
PROGERR, SIZERR, PGAERR, PGSERR, MISSERR (Program error flags),
WRPERR (Protection error flag)
In this case, if the error interrupt enable bit ERRIE is set in the
(FLASH_SR), an interrupt is generated and the operation error flag OPERR is set in the
FLASH_SR register.
Note: If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write requests.
Programming and caches
If a Flash memory write access concerns some data in the data cache, the Flash write
access modifies the data in the Flash memory and the data in the cache.
If an erase operation in Flash memory also concerns data in the data or instruction cache,
you have to make sure that these data are rewritten before they are accessed during code
execution. If this cannot be done safely, it is recommended to flush the caches by setting the
DCRST and ICRST bits in the
Note: The I/D cache should be flushed only when it is disabled (I/DCEN = 0).
3.3.8

Read-while-write (RWW)

The Flash memory is divided into two banks allowing read-while-write operations. This
feature allows to perform a read operation from one bank while an erase or program
operation is performed to the other bank.
Note: Write-while-write operations are not allowed. As an exampled, It is not possible to perform
an erase operation on one bank while programming the other one.
Read from bank 1 while page erasing in bank 2 (or vice versa)
While executing a program code from bank 1, it is possible to perform a page erase
operation on bank 2 (and vice versa). Follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
status register (FLASH_SR)
in bank 1 or bank 2).
2. Set PER bit, PSB to select the page and BKER to select the bank in the
register
3. Set the STRT bit in the FLASH_CR register.
4. Wait for the BSY bit to be cleared (or use the EOP interrupt).
Read from bank 1 while mass erasing bank 2 (or vice versa)
While executing a program code from bank 1, it is possible to perform a mass erase
operation on bank 2 (and vice versa). Follow the procedure below:
90/1693
When FSTPG bit is set for more than 7µs which generates a time-out detection.
When the row fast programming has been interrupted by a MISSERR, PGAERR,
WRPERR or SIZERR.
Flash control register
(FLASH_CR).
DocID024597 Rev 3
(FLASH_CR).
(BSY is active when erase/program operation is on going
RM0351
Flash status register
Flash control
Flash