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RM0351
27.4.19
TIM2 option register 1 (TIM2_OR1)
Address offset: 0x50
Reset value: 0x0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:2 TI4_RMP[1:0]: Input Capture 4 remap
Bit 1 ETR1_RMP: External trigger remap
Bit 0 ITR1_RMP: Internal trigger 1 remap
27.4.20
TIM3 option register 1 (TIM3_OR1)
Address offset: 0x50
Reset value: 0x0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bits 1:0 TI1_RMP[1:0]: Input Capture 1 remap
27.4.21
TIM2 option register 2 (TIM2_OR2)
Address offset: 0x60
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
00: TIM2 input capture 4 is connected to I/O
01: TIM2 input capture 4 is connected to COMP1_OUT
10: TIM2 input capture 4 is connected to COMP2_OUT
11: TIM2 input capture 4 is connected to logical OR between COMP1_OUT and
COMP2_OUT
0: TIM2_ETR is connected to I/O
1: TIM2_ETR is connected to LSE
0: TIM2_ITR1 is connected to TIM8_TRGO
1: TIM2_ITR1 is connected to OTG_FS SOF
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
00: TIM3 input capture 1 is connected to I/O
01: TIM3 input capture 1 is connected to COMP1_OUT
10: TIM3 input capture 1 is connected to COMP2_OUT
11: TIM3 input capture 1 is connected to logical OR between COMP1_OUT and
COMP2_OUT
DocID024597 Rev 3
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
ETR1_
Res.
TI4_RMP[1:0]
RMP
rw
rw
rw
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
Res.
Res.
Res.
TI1_RMP[1:0]
rw
16
Res.
0
ITR1_
RMP
rw
16
Res.
0
rw
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