ST STM32L4x6 Reference Manual page 621

RM0351
Analog watchdog conversions on input channels are independent from standard
conversions. In this case, the analog watchdog uses its own filters and signal processing on
each input channel independently from the main injected or regular conversions. Analog
watchdog conversions are performed in a continuous mode on the selected input channels
in order to watch channels also when main injected or regular conversions are paused
(RCIP = 0, JCIP = 0).
There are high and low threshold registers which are compared with given data values (set
by AWHT[23:0] bits in DFSDMx_AWHTR register and by AWLT[23:0] bits in
DFSDMx_AWLTR register).
Input data into analog watchdog selection and features:
• from final output data register (AWFSEL=0):
–
–
–
–
–
•
from any of serial data receiver outputs (AWFSEL=1):
–
–
–
–
In case of input channels monitoring (AWFSEL=1), the data for comparison to threshold is
taken from channels selected by AWDCH[7:0] field (DFSDMx_CR2 register). Each of the
selected channels filter result is compared to one threshold value pair (AWHT[23:0] /
AWLT[23:0]). In this case, only higher 16 bits (AWHT[23:8] / AWLT[23:8]) define the 16-bit
threshold compared with the analog watchdog filter output because data coming from the
analog watchdog filter is up to a 16-bit resolution. Bits AWHT[7:0] / AWLT[7:0] are not taken
into comparison in this case (AWFSEL=1).
Parameters of the analog watchdog filter configuration for each input channel are set in
DFSDM_AWSCDyR register (filter order AWFORD[1:0] and filter oversampling ratio
AWFOSR[4:0]).
Each input channel has its own comparator which compares the analog watchdog data
(from analog watchdog filter) with analog watchdog threshold values (AWHT/AWLT). When
several channels are selected (field AWDCH[7:0] field of DFSDMx_CR2 register), several
comparison requests may be received simultaneously. In this case, the channel request with
the lowest number is managed first and then continuing to higher selected channels. For
each channel, the result can be recorded in a separate flag (fields AWHTF[7:0], AWLTF[7:0]
of DFSDMx_AWSR register). Each channel request is executed in 8 DFSDM clock cycles.
So, the bandwidth from each channel is limited to 8 DFSDM clock cycles (if AWDCH[7:0] =
0xFF). Because the maximum input channel sampling clock frequency is the DFSDM clock
frequency divided by 4, the configuration AWFOSR = 0 (analog watchdog filter is bypassed)
high resolution (up to 24-bits)
slow response time - not good for fast response (e.g overcurrent)
for comparison, final data is taken after offset data correction and bit shifting
final data is watched only when main regular or injected conversions are
converted
can be used in case of parallel input data source (DATMPX[1:0] ≠ 0 in
DFSDM_CHCFGyR1 register)
through own analog watchdog Sinc
oversampling ratio (1..32) and filter order (1..3) (see AWFOSR[4:0] and
AWFORD[1:0] bits setting in DFSDM_AWSCDyR register)
lower resolution (up to 16-bit)
fast response time - for applications which require a fast response (e.g
overcurrent, overvoltage detection)
data is watched in continuous mode independently from main regular or injected
conversions
DocID024597 Rev 3
Digital filter for sigma delta modulators (DFSDM)
x
channel filters with configurable
621/1693
657