Dfsdm Filter Control Register (Dfsdmx_Fcr) - ST STM32L4x6 Reference Manual

RM0351
Bit 3 CLRROVRF: Clear the regular conversion overrun flag
0: Writing '0' has no effect
1: Writing '1' clears the ROVRF bit in the DFSDMx_ISR register
Bit 2 CLRJOVRF: Clear the injected conversion overrun flag
0: Writing '0' has no effect
1: Writing '1' clears the JOVRF bit in the DFSDMx_ISR register
Bits 1:0 Reserved, must be kept at reset value.
Note: The bits of DFSDMx_ICR are always read as '0'.
21.7.5 DFSDM injected channel group selection register
(DFSDMx_JCHGR)
Address offset: 0x100 * (x+1) + 0x010, x = 0...3
Reset value: 0x0000 0001
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 JCHG[7:0]: Injected channel group selection
JCHG[y]=0: channel y is not part of the injected group
JCHG[y]=1: channel y is part of the injected group
If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel
(channel 0, if selected) is converted first and the sequence ends at the highest selected channel.
If JSCAN=0, then only one channel is converted from the selected channels, and the channel
selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to
the lowest selected channel.
At least one channel must always be selected for the injected group. Writes causing all JCHG bits to
be zero are ignored.
21.7.6

DFSDM filter control register (DFSDMx_FCR)

Address offset: 0x100 * (x+1) + 0x014, x = 0...3
Reset value: 0x0000 0000
31 30 29
FORD[2:0] Res.
rw rw rw
15 14 13
Res. Res. Res. Res.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
28 27 26 25
Res. Res.
rw
12 11 10 9
Res. Res. Res.
DocID024597 Rev 3
Digital filter for sigma delta modulators (DFSDM)
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res.
rw rw rw
24 23 22 21
FOSR[9:0]
rw rw rw rw
8 7 6 5
Res.
rw rw rw
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
JCHG[7:0]
rw rw rw rw
20 19 18 17
rw rw rw rw
4 3 2 1
IOSR[7:0]
rw rw rw rw
16
Res.
0
rw
16
rw
0
rw
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