Reset And Clock Control (Rcc); Reset; Power Reset; System Reset - ST STM32L4x6 Reference Manual

RM0351
6

Reset and clock control (RCC)

6.1

Reset

There are three types of reset, defined as system reset, power reset and backup domain
reset.
6.1.1

Power reset

A power reset is generated when one of the following events occurs:
1. a Brown-out reset (BOR).
2. when exiting from Standby mode.
3. when exiting from Shutdown mode.
A Brown-out reset, including power-on or power-down reset (POR/PDR), sets all registers to
their reset values except the Backup domain.
When exiting Standby mode, all registers in the V
Registers outside the V
control) are not impacted.
When exiting Shutdown mode, a Brown-out reset is generated, resetting all registers except
those in the Backup domain.
6.1.2

System reset

A system reset sets all registers to their reset values except the reset flags in the clock
control/status register (RCC_CSR) and the registers in the Backup domain.
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog event (WWDG reset)
3. Independent watchdog event (IWDG reset)
4. A firewall event (FIREWALL reset)
5. A software reset (SW reset) (see
6. Low-power mode security reset (see
7. Option byte loader reset (see
8. A Brown-out reset
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each internal reset
source. In case of an external reset, the reset pulse is generated while the NRST pin is
asserted low.
In case on an internal reset, the internal pull-up R
power consumption through the pull-up resistor.
domain (RTC, WKUP, IWDG, and Standby/Shutdown modes
CORE
Option byte loader
Section 6.4.30: Control/status register
DocID024597 Rev 3
Reset and clock control (RCC)
domain are set to their reset value.
CORE
Software reset)
Low-power mode security
reset)
(RCC_CSR)).
is deactivated in order to save the
PU
reset)
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