Gpio Port Input Data Register (Gpiox_Idr) (X = A..h) - ST STM32L4x6 Reference Manual

General-purpose I/Os (GPIO)
7.4.5

GPIO port input data register (GPIOx_IDR) (x = A..H)

Address offset: 0x10
Reset value: 0x0000 XXXX (where X means undefined)
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
ID15 ID14 ID13 ID12
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 IDy: Port input data bit (y = 0..15)
These bits are read-only. They contain the input value of the corresponding I/O port.
7.4.6 GPIO port output data register (GPIOx_ODR) (x = A..H)
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
OD15 OD14 OD13 OD12
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ODy: Port output data bit (y = 0..15)
These bits can be read and written by software.
Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the
7.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..H)
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
BR15 BR14 BR13 BR12
w w w
15 14 13
BS15 BS14 BS13 BS12
w w w
266/1693
27 26 25
Res. Res. Res.
11 10 9
ID11 ID10 ID9
r r r r
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
OD11 OD10 OD9
rw rw rw rw
GPIOx_BSRR or GPIOx_BRR registers (x = A..F).
28 27 26 25
BR11 BR10 BR9
w w w w
12 11 10 9
BS11 BS10 BS9
w w w w
DocID024597 Rev 3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
ID8 ID7 ID6 ID5
r r r
24 23 22
Res. Res. Res. Res.
8 7 6
OD8 OD7 OD6 OD5
rw rw rw
24 23 22
BR8 BR7 BR6 BR5
w w w
8 7 6
BS8 BS7 BS6 BS5
w w w
20 19 18
Res. Res. Res.
4 3 2
ID4 ID3 ID2
r r r r
21 20 19 18
Res. Res. Res.
5 4 3 2
OD4 OD3 OD2
rw rw rw rw
21 20 19 18
BR4 BR3 BR2
w w w w
5 4 3 2
BS4 BS3 BS2
w w w w
RM0351
17 16
Res. Res.
1 0
ID1 ID0
r r
17 16
Res. Res.
1 0
OD1 OD0
rw rw
17 16
BR1 BR0
w w
1 0
BS1 BS0
w w