Table 155. Tim2/Tim3/Tim4/Tim5 Register Map And Reset Values; Timx Register Map - ST STM32L4x6 Reference Manual

RM0351
27.4.23

TIMx register map

TIMx registers are mapped as described in the table below:

Table 155. TIM2/TIM3/TIM4/TIM5 register map and reset values

Offset Register
TIMx_CR1
0x00
Reset value
TIMx_CR2
0x04
Reset value
TIMx_SMCR
0x08
Reset value
TIMx_DIER
0x0C
Reset value
TIMx_SR
0x10
Reset value
TIMx_EGR
0x14
Reset value
TIMx_CCMR1
Output
Compare mode
Reset value
0x18
TIMx_CCMR1
Input Capture
mode
Reset value
TIMx_CCMR2
Output
Compare mode
Reset value
0x1C
TIMx_CCMR2
Input Capture
mode
Reset value
TIMx_CCER
0x20
Reset value
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
0
0 0
0 0
DocID024597 Rev 3
CKD
[1:0]
0 0
ETPS
ETF[3:0]
[1:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0
OC2M CC2S
[2:0] [1:0]
0 0 0 0 0 0 0 0
IC2
CC2S
IC2F[3:0] PSC
[1:0]
[1:0]
0 0 0 0 0 0 0 0
OC4M CC4S
[2:0] [1:0]
0 0 0 0 0 0 0 0
IC4
CC4S
IC4F[3:0] PSC
[1:0]
[1:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0
CMS
[1:0]
0 0 0 0 0 0 0 0
MMS[2:0]
0 0 0 0 0
TS[2:0] SMS[2:0]
0 0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
OC1M CC1S
[2:0] [1:0]
0 0 0 0 0 0 0 0
IC1
CC1S
IC1F[3:0] PSC
[1:0]
[1:0]
0 0 0 0 0 0 0 0
OC3M CC3S
[2:0] [1:0]
0 0 0 0 0 0 0 0
IC3
CC3S
IC3F[3:0] PSC
[1:0]
[1:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0
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