Tim2/Tim3/Tim4/Tim5 Registers - ST STM32L4x6 Reference Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
27.4

TIM2/TIM3/TIM4/TIM5 registers

Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
27.4.1 TIMx control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 UIFREMAP: UIF status bit remapping
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (ETR, TIx),
Bit 7 ARPE: Auto-reload preload enable
Bits 6:5 CMS: Center-aligned mode selection
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
Bit 4 DIR: Direction
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
902/1693
Section 1.1 for a list of abbreviations used in register descriptions.
12 11 10 9
UIF
RE- Res. CKD[1:0]
MAP
rw rw
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
00: t = t
DTS CK_INT
01: t = 2 × t
DTS CK_INT
10: t = 4 × t
DTS CK_INT
11: Reserved
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
the counter is enabled (CEN=1)
0: Counter used as upcounter
1: Counter used as downcounter
mode.
8 7 6
ARPE CMS
rw rw rw
DocID024597 Rev 3
5 4 3 2
DIR OPM URS
rw rw rw rw
RM0351
1 0
UDIS CEN
rw rw