Peripherals Independent Clock Configuration Register (Rcc_Ccipr) - ST STM32L4x6 Reference Manual

RM0351
6.4.28

Peripherals independent clock configuration register (RCC_CCIPR)

Address: 0x88
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access
31 30 29
SWP
DFSDM
MI1
ADCSEL[1:0]
SEL
SEL
rw rw rw
15 14 13
I2C2SEL[1:0] I2C1SEL[1:0]
rw rw rw
Bit 31 DFSDMSEL: DFSDM clock source selection
Bit 30 SWPMI1SEL: SWPMI1 clock source selection
Bits 29:28 ADCSEL[1:0]: ADCs clock source selection
Bits 27:26 CLK48SEL[1:0]: 48 MHz clock source selection
Bits 25:24 SAI2SEL[1:0]: SAI2 clock source selection
Caution:
28 27 26 25
CLK48SEL[1:0] SAI2SEL[1:0]
rw rw rw rw
12 11 10 9
LPUART1SEL UART5SEL
[1:0]
rw rw rw rw
This bit is set and cleared by software to select the DFSDM clock source.
0: PCLK selected as DFSDM clock
1: System clock (SYSCLK) used as DFSDM clock
This bit is set and cleared by software to select the SWPMI1 clock source.
0: PCLK selected as SWPMI1 clock
1: HSI16 clock selected as SWPMI1 clock
These bits are set and cleared by software to select the clock source used by the ADC
interface.
00: No clock selected
01: PLLSAI1 "R" clock (PLLADC1CLK) selected as ADCs clock
10: PLLSAI2 "R" clock (PLLADC2CLK) selected as ADCs clock
11: System clock selected as ADCs clock
These bits are set and cleared by software to select the 48 MHz clock source used by USB
OTG FS, RNG and SDMMC.
00: No clock selected
01: PLLSAI1 "Q" clock (PLL48M2CLK) selected as 48 MHz clock
10: PLL "Q" clock (PLL48M1CLK) selected as 48 MHz clock
11: MSI clock selected as 48 MHz clock
These bits are set and cleared by software to select the SAI2 clock source.
00: PLLSAI1 "P" clock (PLLSAI1CLK) selected as SAI2 clock
01: PLLSAI2 "P" clock (PLLSAI2CLK) selected as SAI2 clock
10: PLL "P" clock (PLLSAI3CLK) selected as SAI2 clock
11: External input SAI2_EXTCLK selected as SAI2 clock
If the selected clock is the external clock, it is not possible to switch to another
clock if the external clock is not present.
24 23 22
SAI1SEL[1:0]
rw rw rw
8 7 6
UART4SEL
[1:0] [1:0]
rw rw rw
DocID024597 Rev 3
Reset and clock control (RCC)
21 20 19 18
LPTIM2SEL[1:0] LPTIM1SEL[1:0
rw rw rw rw
5 4 3
USART3SEL USART2SEL
[1:0] [1:0]
rw rw rw rw
17 16
I2C3SEL[1:0]
rw rw
2 1 0
USART1SEL
[1:0]
rw rw
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