Tim1/Tim8 Capture/Compare Enable Register (Timx_Ccer) - ST STM32L4x6 Reference Manual

RM0351
Input capture mode
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:12 IC4F: Input capture 4 filter
Bits 11:10 IC4PSC: Input capture 4 prescaler
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER).
Bits 7:4 IC3F: Input capture 3 filter
Bits 3:2 IC3PSC: Input capture 3 prescaler
Bits 1:0 CC3S: Capture/compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER).
26.4.9

TIM1/TIM8 capture/compare enable register (TIMx_CCER)

Address offset: 0x20
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
CC4NP Res. CC4P CC4E
rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 CC6P: Capture/Compare 6 output polarity
Refer to CC1P description
Bit 20 CC6E: Capture/Compare 6 output enable
Refer to CC1E description
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CC5P: Capture/Compare 5 output polarity
Refer to CC1P description
Bit 16 CC5E: Capture/Compare 5 output enable
Refer to CC1E description
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
28 27 26 25
Res. Res. Res.
12 11 10 9
CC3NP CC3NE CC3P
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
CC3E CC2NP CC2NE
rw rw rw
DocID024597 Rev 3
Advanced-control timers (TIM1/TIM8)
21 20 19
CC6P CC6E Res.
rw rw
5 4 3
CC2P CC2E CC1NP CC1NE
rw rw rw
18 17 16
Res. CC5P CC5E
rw rw
2 1 0
CC1P CC1E
rw rw rw
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