Figure 228. 3-Phase Combined Pwm Signals With Multiple Trigger Pulses Per Period; Complementary Outputs And Dead-Time Insertion - ST STM32L4x6 Reference Manual

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Figure 228. 3-phase combined PWM signals with multiple trigger pulses per period

The TRGO2 waveform shows how the ADC can be synchronized on given 3-phase PWM
signals. Please refer to
26.3.15

Complementary outputs and dead-time insertion

The advanced-control timers (TIM1/TIM8) can output two complementary signals and
manage the switching-off and the switching-on instants of the outputs.
This time is generally known as dead-time and you have to adjust it depending on the
devices you have connected to the outputs and their characteristics (intrinsic delays of level-
shifters, delays due to power switches...)
You can select the polarity of the outputs (main output OCx or complementary OCxN)
independently for each output. This is done by writing to the CCxP and CCxNP bits in the
TIMx_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several
control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,
OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to
Table 149: Output control bits for complementary OCx and OCxN channels with break
feature on page 832
switching to the idle state (MOE falling down to 0).
Section 26.3.27: ADC synchronization
for more details. In particular, the dead-time is activated when
DocID024597 Rev 3
Advanced-control timers (TIM1/TIM8)
for more details.
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