Power Status Register 2 (Pwr_Sr2) - ST STM32L4x6 Reference Manual

Power control (PWR)
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 WUFI: Wakeup flag internal
Bits 14:9 Reserved, must be kept at reset value.
Bit 8 SBF: Standby flag
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 WUF5: Wakeup flag 5
Bit 3 WUF4: Wakeup flag 4
Bit 2 WUF3: Wakeup flag 3
Bit 1 WUF2: Wakeup flag 2
Bit 0 WUF1: Wakeup flag 1
5.4.6

Power status register 2 (PWR_SR2)

Address offset: 0x14
Reset value: 0x0000 0000. This register is partially reset when exiting Standby/Shutdown
modes.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
PVMO PVMO PVMO PVMO
4 3 2
r r r
166/1693
This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all
internal wakeup sources are cleared.
This bit is set by hardware when the device enters the Standby mode and is cleared by
setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the
system reset.
0: The device did not enter the Standby mode
1: The device entered the Standby mode
This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by
writing '1' in the CWUF5 bit of the PWR_SCR register.
This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by
writing '1' in the CWUF4 bit of the PWR_SCR register.
This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by
writing '1' in the CWUF3 bit of the PWR_SCR register.
This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by
writing '1' in the CWUF2 bit of the PWR_SCR register.
This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by
writing '1' in the CWUF1 bit of the PWR_SCR register.
27 26 25
Res. Res. Res.
11 10 9
REGLP
PVDO VOSF
1 F
r r r r
24 23 22
Res. Res. Res.
8 7 6
REGLP
Res. Res.
S
r
DocID024597 Rev 3
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
RM0351
17 16
Res. Res.
1 0
Res. Res.