Figure 297. Triggering Tim3 And Tim2 With Tim3 Ti1 Input; Dma Burst Mode - ST STM32L4x6 Reference Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
aligned, TIM3 must be configured in Master/Slave mode (slave with respect to TI1, master
with respect to TIM2):
1. Configure TIM3 master mode to send its Enable as trigger output (MMS=001 in the
TIM3_CR2 register).
2. Configure TIM3 slave mode to get the input trigger from TI1 (TS=100 in the
TIM3_SMCR register).
3. Configure TIM3 in trigger mode (SMS=110 in the TIM3_SMCR register).
4. Configure the TIM3 in Master/Slave mode by writing MSM=1 (TIM3_SMCR register).
5. Configure TIM2 to get the input trigger from TIM3 (TS=000 in the TIM2_SMCR
register).
6. Configure TIM2 in trigger mode (SMS=110 in the TIM2_SMCR register).
When a rising edge occurs on TI1 (TIM3), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note: In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but you can easily insert an offset between them by
writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on TIM3.
Note: The clock of the slave timer must be enabled prior to receive events from the master timer,
and must not be changed on-the-fly while triggers are received from the master timer.
27.3.20

DMA burst mode

The TIMx timers have the capability to generate multiple DMA requests upon a single event.
The main purpose is to be able to re-program part of the timer multiple times without
software overhead, but it can also be used to read several registers in a row, at regular
intervals.
The DMA controller destination is unique and must point to the virtual register TIMx_DMAR.
On a given timer event, the timer launches a sequence of DMA requests (burst). Each write
into the TIMx_DMAR register is actually redirected to one of the timer registers.
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Figure 297. Triggering TIM3 and TIM2 with TIM3 TI1 input

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