Tim15 Counter (Tim15_Cnt) - ST STM32L4x6 Reference Manual

RM0351
28.5.9

TIM15 counter (TIM15_CNT)

Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
UIF
Res Res
CPY
r
15 14 13
rw rw rw
Bit 31 UIFCPY: UIF Copy
This bit is a read-only copy of the UIF bit in the TIMx_ISR register.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
28.5.10 TIM15 prescaler (TIM15_PSC)
Address offset: 0x28
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (CK_CNT) is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger
controller when configured in "reset mode").
28.5.11 TIM15 auto-reload register (TIM15_ARR)
Address offset: 0x2C
Reset value: 0xFFFF
15 14 13
rw rw rw
Bits 15:0 ARR[15:0]: Prescaler value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the
and behavior.
The counter is blocked while the auto-reload value is null.
28 27 26 25
Res Res Res Res
12 11 10 9
rw rw rw rw
12 11 10 9
rw rw rw rw
12 11 10 9
rw rw rw rw
Section 28.4.1: Time-base unit on page 934
General-purpose timers (TIM15/16/17)
24 23 22
Res Res Res
8 7 6
CNT[15:0]
rw rw rw
8 7 6
PSC[15:0]
rw rw rw
8 7 6
ARR[15:0]
rw rw rw
DocID024597 Rev 3
21 20
19 18
Res Res Res Res
5 4 3 2
rw rw rw rw
5 4 3 2
rw rw rw rw
/ (PSC[15:0] + 1).
CK_PSC
5 4 3 2
rw rw rw rw
for more details about ARR update
17 16
Res Res
1 0
rw rw
1 0
rw rw
1 0
rw rw
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