Tim15 Option Register 1 (Tim15_Or1) - ST STM32L4x6 Reference Manual

General-purpose timers (TIM15/16/17)
Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located at the address
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA
transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
28.5.18

TIM15 option register 1 (TIM15_OR1)

Address offset: 0x50
Reset value: 0x0000
31 30 29
Res Res Res
15 14 13
Res Res Res
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:1 ENCODER_MODE[1:0]: Encoder mode
00: No redirection
01:TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
10:TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
11:TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
Bit 0 TI1_RMP: Input capture 1 remap
0: TIM15 input capture 1 is connected to I/O
1: TIM15 input capture 1 is connected to LSE
28.5.19 TIM15 option register 2 (TIM15_OR2)
Address offset: 0x60
Reset value: 0x0000 0001
31 30 29
Res Res Res
15 14 13
Res Res Res
Bits 31:12 Reserved, must be kept at reset value.
984/1693
(TIMx_CR1 address) + (DBA + DMA index) x 4
28 27 26 25
Res Res Res Res
12 11 10 9
Res Res Res Res
28 27 26 25
Res Res Res Res
12 11 10 9
BKCM BKCM
Res BKINP
P2P P1P
rw rw rw
24 23 22
Res Res Res
8 7 6
Res Res Res
24 23 22
Res Res Res
8 7 6
BKDF
Res Res
BK0E
rw
DocID024597 Rev 3
21 20 19 18
Res Res Res Res
5 4 3 2
ENCODER_
Res Res Res
MODE[1:0]
rw
21 20 19 18
Res Res Res Res
5 4 3 2
BKCM
Res. Res. Res.
P2E
rw
RM0351
17 16
Res Res
1 0
TI1_
RMP
rw rw
17 16
Res Res
1 0
BKCM
BKINE
P1E
rw rw