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Extended interrupts and events controller (EXTI)
12.5.10
Falling trigger selection register 2 (EXTI_FTSR2)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these
lines. If a falling edge on a configurable interrupt line occurs during a write operation to the
EXTI_FTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.
12.5.11
Software interrupt event register 2 (EXTI_SWIER2)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
334/1693
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Bits 7:3 FTx: Falling trigger event configuration bit of line x (x = 35 to 38)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
Bits 2:0 Reserved, must be kept at reset value.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Bit 7 SWIx: Software interrupt on line x (x = 35 to 38)
If the interrupt is enabled on this line in EXTI_IMR, writing a '1' to this bit when it
is at '0' sets the corresponding pending bit of EXTI_PR resulting in an interrupt
request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1'
to the bit).
Bits 2:0 Reserved, must be kept at reset value.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
FT38
rw
24
23
22
Res.
Res.
Res.
8
7
6
SWI
Res.
Res.
38
rw
DocID024597 Rev 3
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
FT37
FT36
FT35
Res.
rw
rw
rw
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
SWI
SWI
SWI
Res.
37
36
35
rw
rw
rw
RM0351
17
16
Res.
Res.
1
0
Res.
Res.
17
16
Res.
Res.
1
0
Res.
Res.
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