Dfsdm Analog Watchdog Low Threshold Register (Dfsdmx_Awltr) - ST STM32L4x6 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
21.7.9 DFSDM analog watchdog high threshold register
(DFSDMx_AWHTR)
Address offset: 0x100 * (x+1) + 0x020, x = 0...3
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:8 AWHT[23:0]: Analog watchdog high threshold
These bits are written by software to define the high threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the
16-bit threshold as compared with the analog watchdog filter output (because data coming from
the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into
comparison in this case.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 BKAWH[3:0]: Break signal assignment to analog watchdog high threshold event
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event
BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
21.7.10

DFSDM analog watchdog low threshold register (DFSDMx_AWLTR)

Address offset: 0x100 * (x+1) + 0x024, x = 0...3
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
644/1693
28 27 26 25
rw rw rw rw
12 11 10 9
AWHT[7:0]
rw rw rw rw
28 27 26 25
rw rw rw rw
12 11 10 9
AWLT[7:0]
rw rw rw rw
DocID024597 Rev 3
24 23 22 21
AWHT[23:8]
rw rw rw rw
8 7 6 5
Res. Res. Res.
rw
24 23 22 21
AWLT[23:8]
rw rw rw rw
8 7 6 5
Res. Res. Res.
rw
20 19 18 17
rw rw rw rw
4 3 2 1
Res. BKAWH[3:0]
rw rw rw
20 19 18 17
rw rw rw rw
4 3 2 1
Res. BKAWL[3:0]
rw rw rw
RM0351
16
rw
0
rw
16
rw
0
rw