Table 42. Stm32L4X6 Vector Table; Interrupt And Exception Vectors - ST STM32L4x6 Reference Manual

Nested vectored interrupt controller (NVIC)
11.3

Interrupt and exception vectors

Type of
priority
- - -
- -3 fixed
- -2 fixed
- -1 fixed
- 0 settable
- 1 settable
- 2 settable
- - -
- 3 settable
- 4 settable
- - -
- 5 settable
- 6 settable
0 7 settable
1 8 settable
2 9 settable
3 10 settable
4 11 settable
5 12 settable
6 13 settable
7 14 settable
8 15 settable
9 16 settable
10 17 settable
11 18 settable
12 19 settable
13 20 settable
320/1693

Table 42. STM32L4x6 vector table

Acronym
- Reserved
Reset Reset
Non maskable interrupt. The RCC Clock
NMI Security System (CSS) is linked to the NMI
vector.
HardFault All classes of fault
MemManage Memory management
BusFault Pre-fetch fault, memory access fault
UsageFault Undefined instruction or illegal state
- Reserved
SVCall System service call via SWI instruction
Debug Monitor
- Reserved
PendSV Pendable request for system service
SysTick System tick timer
WWDG Window Watchdog interrupt
PVD/PVM1/PVM2/PVM3/PVM4 through EXTI
PVD_PVM
lines 16/35/36/37/38 interrupts
RTC_TAMP_STAMP RTC Tamper or TimeStamp /CSS on LSE
/CSS_LSE through EXTI line 19 interrupts
RTC Wakeup timer through EXTI line 20
RTC_WKUP
interrupt
FLASH Flash global interrupt
RCC RCC global interrupt
EXTI0 EXTI Line0 interrupt
EXTI1 EXTI Line1 interrupt
EXTI2 EXTI Line2 interrupt
EXTI3 EXTI Line3 interrupt
EXTI4 EXTI Line4 interrupt
DMA1_CH1 DMA1 channel 1 interrupt
DMA1_CH2 DMA1 channel 2 interrupt
DMA1_CH3 DMA1 channel 3 interrupt
DocID024597 Rev 3
Description
RM0351
Address
0x0000 0000
0x0000 0004
0x0000 0008
0x0000 000C
0x0000 0010
0x0000 0014
0x0000 0018
0x0000 001C -
0x0000 0028
0x0000 002C
0x0000 0030
0x0000 0034
0x0000 0038
0x0000 003C
0x0000 0040
0x0000 0044
0x0000 0048
0x0000 004C
0x0000 0050
0x0000 005C
0x0000 005C
0x0000 005C
0x0000 0060
0x0000 0064
0x0000 0068
0x0000 006C
0x0000 0070
0x0000 0074