Flash Ecc Register (Flash_Eccr) - ST STM32L4x6 Reference Manual

Embedded Flash memory (FLASH)
Bits 10:3 PNB[7:0]: Page number selection
3.7.7

Flash ECC register (FLASH_ECCR)

Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
31 30 29
ECCD ECCC Res. Res.
rc_w1 rc_w1
15 14 13
r r r
Bits 29:25 Reserved, must be kept at reset value.
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These bits select the page to erase:
If BKER = 0:
00000000: page 0
00000001: page 1
...
11111111: page 255
If BKER=1
00000000: page 256
00000001: page 257
...
11111111: page 511
Bit 2 MER1: Bank 1 Mass erase
This bit triggers the bank 1 mass erase (all bank 1 user pages) when set.
Bit 1 PER: Page erase
0: page erase disabled
1: page erase enabled
Bit 0 PG: Programming
0: Flash programming disabled
1: Flash programming enabled
28 27 26 25
Res. Res. Res.
12 11 10 9
r r r r
Bit 31 ECCD: ECC detection
Set by hardware when two ECC errors have been detected. When this bit is set,
a NMI is generated
Cleared by writing 1.
Bit 30 ECCD: ECC correction
Set by hardware when one ECC error has been detected and corrected. An
interrupt is generated if ECCIE is set.
Cleared by writing 1.
DocID024597 Rev 3
24 23 22
ECCC
Res. Res. Res.
IE
rw
8 7 6
ADDR_ECC[15:0]
r r r
21 20 19 18
BK
SYSF_
ADDR_ECC[18:16]
ECC
_ECC
r r r
5 4 3 2
r r r r
RM0351
17 16
r r
1 0
r r